Datasheet

KSZ8081RNA/RND
 
8.0 RESET CIRCUIT
 

FIGURE 8-1:
VDDIO
D1: 1N4148
D1
R 10K
KSZ8081RNA/RND
RST#
C 10μF
RECOMMENDED RESET CIRCUIT
 









      

   






FIGURE 8-2:
VDDIO
KSZ8081RNA/RND
D1
R 10K
RST#
C 10μF
D2
CPU/FPGA
RST_OUT_n
D1, D2: 1N4148
RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT