Datasheet

KSZ8081MNX/RNB
DS00002202C-page 6 2016-2018 Microchip Technology Inc.
8 XO O
Crystal feedback for 25 MHz crystal.
This pin is a no connect if an oscillator or external clock source is
used.
9 XI I Crystal / Oscillator / External Clock Input. 25 MHz ±50 ppm.
10 REXT I
Set PHY transmit output current. Connect a 6.49 k resistor to
ground on this pin.
11 MDIO Ipu/Opu
Management Interface (MII) Data I/O This pin has a weak pull-up, is
open-drain, and requires an external 1.0 k pull-up resistor.
12 MDC Ipu
Management Interface (MII) Clock Input. This clock pin is synchro-
nous to the MDIO data pin.
13 PHYAD0 Ipu/O
MII Mode: MII Receive Data Output[3].
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[0] at the de-assertion of reset.
See the Strap-In Options – KSZ8081MNX section for details.
14 PHYAD1 Ipd/O
MII Mode: MII Receive Data Output[2]
(Note 2-2)
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[1] at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
15
RXD1/
PHYAD2
Ipd/O
MII Mode: MII Receive Data Output[1] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as PHY-
ADDR[2] at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
16
RXD0/
DUPLEX
Ipu/O
MII Mode: MII Receive Data Output[0] (Note 2-2).
Config Mode: The pull-up/pull-down value is latched as DUPLEX at
the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital V
DD
.
18
RXDV/
CONFIG2
Ipd/O
MII Mode: MII Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2
at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
19
RXC/
B-CAST_OFF
Ipd/O
MII Mode: MII Receive Clock Output.
Config Mode: The pull-up/pull-down value is latched as B-
CAST_OFF at the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
20
RXER/
ISO
Ipd/O
MII mode: MII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at
the de-assertion of reset.
See the section Strap-In Options – KSZ8081MNX for details.
TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX (CONTINUED)
Pin
Number
Name
Buffer
Type
(Note 2-1)
Description