Datasheet

 2016-2018 Microchip Technology Inc. DS00002202C-page 55
KSZ8081MNX/RNB
7.10 Reset Circuit
Figure 7-11 shows a reset circuit recommended for powering up the KSZ8081MNX/RNB if reset is triggered by the
power supply.
FIGURE 7-11: RECOMMENDED RESET CIRCUIT
Figure 7-12 Shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2
is used if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other.
If different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same
VDDIO voltage.
FIGURE 7-12: RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
OUTPUT
VDDIO
D1: 1N4148
D1
R 10K
KSZ8081MNX/RNB
RST#
C 10μF
VDDIO
KSZ8081MNX/RNB
D1
R 10K
RST#
C 10μF
D2
CPU/FPGA
RST_OUT_N
D1, D2: 1N4148