Datasheet

KSZ8081MNX/RNB
DS00002202C-page 54 2016-2018 Microchip Technology Inc.
7.9 Power-up/Reset Timing
The KSZ8081MNX/RNB reset timing requirement is summarized in Figure 7-10 and Table 7-10.
FIGURE 7-10: POWER-UP/RESET TIMING
The supply voltage (V
DDIO
and V
DDA_3.3
) power-up waveform should be monotonic. The 300 µs minimum rise time is
from 10% to 90%.
For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are read
and updated at the de-assertion of reset.
After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) inter-
face.
TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS
Parameter Description Min. Max. Units
t
VR
Supply voltage (V
DDIO
, V
DDA_3.3
) rise time 300 µs
t
SR
Stable supply voltage (V
DDIO,
V
DDA_3.3
) to reset
high
10 ms
t
CS
Configuration setup time 5 ns
t
CH
Configuration hold time 5 ns
t
RC
Reset to strap-in pin output 6 ns
SUPPLY
VOLTAGES
RST#
STRAP-IN
VALUE
STRAP-IN /
OUTPUT PIN
t
VR
t
SR
t
CS
t
CH
t
RC