Datasheet

 2016-2018 Microchip Technology Inc. DS00002202C-page 49
KSZ8081MNX/RNB
7.3 MII Receive Timing (10BASE-T)
FIGURE 7-3: MII RECEIVE TIMING (10BASE-T)
t
HD1
TXD[3:0] hold from rising edge of TXC 0
— —
ns
t
HD2
TXEN hold from rising edge of TXC 0
— —
ns
t
CRS1
TXEN high to CRS asserted latency 600
—
ns
t
CRS2
TXEN low to CRS de-asserted latency 1.0
—
µs
TABLE 7-3: MII RECEIVE TIMING (10BASE-T) PARAMETERS
Timing Parameters Description Min. Typ. Max. Units
t
P
RXC period — 400 — ns
t
WL
RXC pulse width low
—
200
—
ns
t
WH
RXC pulse width high
—
200
—
ns
t
OD
(RXDV, RXD[3:0], RXER) output
delay from rising edge of RXC
— 205 —
ns
t
RLAT
CRS to (RXDV, RXD[3:0]) latency
— 7.2 —
µs
TABLE 7-2: MII TRANSMIT TIMING (10BASE-T) PARAMETERS (CONTINUED)
Timing Parameters Description Min. Typ. Max. Units
CRS
RXDV
RXD[3:0]
RXER
RXC
t
RLAT
t
OD
t
P
t
WL
t
WH