Datasheet
2016-2018 Microchip Technology Inc. DS00002202C-page 41
KSZ8081MNX/RNB
Register 17h – Operation Mode Strap Status
17.15:13
PHYAD[2:0]
Strap-In Status
[000] = Strap to PHY Address 0
[001] = Strap to PHY Address 1
[010] = Strap to PHY Address 2
[011] = Strap to PHY Address 3
[100] = Strap to PHY Address 4
[101] = Strap to PHY Address 5
[110] = Strap to PHY Address 6
[111] = Strap to PHY Address 7
RO —
17.12:10 Reserved Reserved RO —
17.9
B-CAST_OFF
Strap-In Status
1 = Strap to B-CAST_OFF
If bit is ‘1’, PHY Address 0 is non-
broadcast.
RO —
17.8 Reserved Reserved RO —
17.7
MII B-to-B
Strap-In Status
1 = Strap to MII back-to-back mode
This bit applies only to
KSZ8081MNX.
RO —
17.6
RMII B-to-B
Strap-In Status
1 = Strap to RMII Back-to-Back
mode
This bit applies only to
KSZ8081RNB.
RO —
17.5
NAND Tree
Strap-In Status
1 = Strap to NAND tree mode RO —
17.4:2 Reserved Reserved RO —
17.1
RMII Strap-In
Status
1 = Strap to RMII mode
This bit applies only to
KSZ8081RNB.
RO —
17.0
MII Strap-In
Status
1 = Strap to MII mode
This bit applies only to
KSZ8081MNX.
RO —
Register 18h – Expanded Control
18.15:12 Reserved Reserved RW 0000
18.11
EDPD
Disabled
Energy-detect power-down mode
1 = Disable
0 = Enable
See also Register 10h, Bit [4] for PLL
off.
RW 1
18.10
100BASE-TX
Latency
1 = MII output is random latency
0 = MII output is fixed latency
For both settings, all bytes of
received preamble are passed to the
MII output.
This bit applies only to
KSZ8081MNX.
RW 0
18.9:7 Reserved Reserved RW 00_0
18.6
10BASE-T
Preamble
Restore
1 = Restore received preamble to MII
output
0 = Remove all seven bytes of pre-
amble before sending frame (starting
with SFD) to MII output
This bit applies only to
KSZ8081MNX,
RW 0
TABLE 4-2: REGISTER DESCRIPTION (CONTINUED)
Address Name Description Mode Default