Datasheet

2016-2018 Microchip Technology Inc. DS00002202C-page 29
KSZ8081MNX/RNB
Note 3-1 KS8081MNX supports partial NAND tree test pins. Ta b le 3-6 lists partial NAND tree test pins. If full
NAND tree testing is required, please use KSZ8091MNX device that supports all the required pins.
3.10.1 NAND TREE I/O TESTING
Use the following procedure to check for faults on the KSZ8081MNX/RNB digital I/O pin connections to the board:
1. Enable NAND tree mode using either hardware (NAND_Tree#, Pin 21) or software (Register 16h, Bit [5]).
2. Use board logic to drive all KSZ8081MNX/RNB NAND tree input pins high.
3. Use board logic to drive each NAND tree input pin, in KSZ8081MNX/RNB NAND tree pin order, as follows:
a) Toggle the first pin (MDIO) from high to low, and verify that the TXD1 pin switches from high to low to indicate
that the first pin is connected properly.
b) Leave the first pin (MDIO) low.
c) Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to
indicate that the second pin is connected properly.
d) eave the first pin (MDIO) and the second pin (MDC) low.
e) Continue with this sequence until all KSZ8081MNX/RNB NAND tree input pins have been toggled.
TABLE 3-6: NAND TREE TEST PIN ORDER FOR KSZ8081MNX
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
21 INTRP Input
23 TXEN Input
30 LED0 Input
24 TXD0 Input
25 TXD1 Output
TABLE 3-7: NAND TREE TEST PIN ORDER FOR KSZ8081RNB
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
21 INTRP Input
23 TXEN Input
31 LED1 Input
30 LED0 Input
24 TXD0 Input
25 TXD1 Output