Datasheet
KSZ8081MNX/RNB
DS00002202C-page 20 2016-2018 Microchip Technology Inc.
3.3 RMII Data Interface (KSZ8081RNB Only)
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It pro-
vides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference
clock).
•10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 2 bits wide, a dibit.
3.3.1 RMII – 25 MHZ CLOCK MODE
The KSZ8081RNB is configured to RMII – 25 MHz clock mode after it is powered up or hardware reset with the following:
•A 25 MHz crystal connected to XI, XO (pins 9, 8), or an external 25 MHz clock source (oscillator) connected to XI.
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 0 (default value) to select 25 MHz clock mode.
3.3.2 RMII – 50 MHZ CLOCK MODE
The KSZ8081RNB is configured to RMII – 50 MHz clock mode after it is powered up or hardware reset with the following:
• An external 50 MHz clock source (oscillator) connected to XI (Pin 9).
• The CONFIG[2:0] strapping pins (pins 18, 29, 28) set to 001.
• Register 1Fh, Bit [7] is set to 1 to select 50 MHz clock mode.
3.3.3 RMII SIGNAL DEFINITION
Table 3-2 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.
3.3.4 REFERENCE CLOCK (REF_CLK)
REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0],
and RX_ER.
For 25 MHz clock mode, the KSZ8081RNB generates and outputs the 50 MHz RMII REF_CLK to the MAC at REF_CLK
(Pin 19).
For 50 MHz clock mode, the KSZ8081RNB takes in the 50 MHz RMII REF_CLK from the MAC or system board at XI
(Pin 9) and leaves the REF_CLK (Pin 19) as a no connect.
TABLE 3-2: RMII SIGNAL DEFINITION
MII Signal Name
Direction
(with respect to PHY,
KSZ8081MNX signal)
Direction
(with respect to MAC)
Description
TXC Output Input
Transmit Clock
(2.5 MHz for 10 Mbps;
25 MHz for 100 Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data[3:0]
RXC Output Input
Receive Clock
(2.5 MHz for 10 Mbps;
25
MHz for 100 Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data[3:0]