Datasheet

KSZ8081MNX/RNB
DS00002202C-page 14 2016-2018 Microchip Technology Inc.
Note 2-1 Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;
output pin otherwise.
Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal
pull-up (see Electrical Characteristics for value).
19 B-CAST_OFF Ipd/O
Broadcast off – for PHY Address 0
Pull-up = PHY Address 0 is set as an unique PHY address
Pull-down (default) = PHY Address 0 is set as a broadcast PHY address
At the de-assertion of reset, this pin value is latched by the chip.
21 NAND_Tree#
Ipu/
Opu
NAND tree mode
Pull-up (default) = Disable
Pull-down = Enable
At the de-assertion of reset, this pin value is latched by the chip.
TABLE 2-4: STRAP-IN OPTIONS (CONTINUED)
Pin
Number
Pin Name
Type
(Note
2-1)
Pin Function