Datasheet
2016-2018 Microchip Technology Inc. DS00002202C-page 13
KSZ8081MNX/RNB
= Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up
(see Electrical Characteristics for value). NC = Pin is not bonded to the die.
Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each
clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the
MAC.
Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each
clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.
2.2 Strap-in Options – KSZ8081RNB
The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive
high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to
unintended high/low states. In this case, external pull-ups (4.7
k) or pull-downs (1.0 k) should be added on these
PHY strap-in pins to ensure that the intended values are strapped-in correctly.
TABLE 2-4: STRAP-IN OPTIONS
Pin
Number
Pin Name
Type
(Note
2-1)
Pin Function
15
14
13
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
PHYAD[2:0] is latched at de-assertion of reset and is configurable to any value
from 0 to 7 with PHY Address 1 as the default value.
PHY Address 0 is assigned by default as the broadcast PHY address, but it can
be assigned as a unique PHY address after pulling the
B-CAST_OFF strapping pin high or writing a ‘1’ to Register 16h, Bit [9].
PHY Address bits [4:3] are set to 00 by default.
18
29
28
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at the de-assertion of reset.
20 ISO Ipd/O
Isolate mode
Pull-up = Enable
Pull-down (default) = Disable
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [10].
31 SPEED Ipu/O
Speed mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [13] as
the speed select, and also is latched into Register 4h (auto-negotiation adver
-
tisement) as the speed capability support.
16 DUPLEX Ipu/O
Duplex mode
Pull-up (default) = Half-duplex
Pull-down = Full-duplex
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [8].
30 NWAYEN Ipu/O
Nway auto-negotiation enable
Pull-up (default) = Enable auto-negotiation
Pull-down = Disable auto-negotiation
At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
CONFIG[2:0] Mode
001 RMII
101 RMII back-to-back
000, 010 – 100, 110, 111 Reserved – not used