Datasheet
KSZ8081MNX/RNB
DS00002202C-page 10 2016-2018 Microchip Technology Inc.
FIGURE 2-2: KSZ8081RNB 32-QFN PIN ASSIGNMENT (TOP VIEW)
TABLE 2-3: PIN DESCRIPTION — KSZ8081RNB
Pin Number Pin Name Type (Note 2-1) Pin Function
1 GND GND Ground
2 VDD_1.2 P
1.2V core V
DD
(power supplied by KSZ8081RNB)
.
Decouple with 2.2 µF and 0.1 µF capacitors to ground.
3 VDDA_3.3 P 3.3V analog V
DD
.
4 RXM I/O Physical receive or transmit signal ( differential).
5 RXP I/O Physical receive or transmit signal (+ differential).
6 TXM I/O Physical transmit or receive signal ( differential).
7 TXP I/O Physical transmit or receive signal (+ differential).
8 XO O
Crystal feedback for 25 MHz crystal. This pin is a no con-
nect if an oscillator or external clock source is used.
9 XI I
25 MHz Mode: 25 MHz ±50 ppm Crystal / Oscillator /
External Clock Input
50 MHz Mode: 50 MHz ±50 ppm Oscillator / External
Clock Input
10 REXT I
Set PHY transmit output current. Connect a 6.49 k
resistor to ground on this pin.
11 MDIO Ipu/Opu
Management Interface (MII) Data I/O. This pin has a
weak pull-up, is open-drain, and requires an external
1.0
k pull-up resistor.
12 MDC Ipu
Management Interface (MII) Clock Input. This clock pin is
synchronous to the MDIO data pin.
13 PHYAD0 Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at
the de-assertion of reset.
See the Strap-in Options – KSZ8081RNB section for
details.
GND
VDD_1.2
VDDA_3.3
RXM
RXP
TXM
TXP
XO
PHYAD0
MDC
MDIO
REXT
XI
PHYAD1
RXD1/PHYAD2
RXD0/DUPLEX
1
2
3
4
5
6
7
8
9101112131415
16
24
23
22
21
20
19
18
17
32 31 30 29 28 27 26
25
TXD0
TXEN
NC
INTRP/NAND_TREE#
RXER/ISO
REF_CLK/B-CAST_OFF
CRS_DV/CONFIG2
VDDIO
CONFIG0
CONFIG1
LED0/NWAYEN
LED1/SPEED
RST#
NC
NC
TXD1
PADDLE
GROUND
(ON BOTTOM OF CHIP)