KSZ8081MNX/RNB 10BASE-T/100BASE-TX Physical Layer Transceiver Features Applications • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver • MII interface support (KSZ8081MNX) • RMII v1.
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KSZ8081MNX/RNB Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 5 3.0 Functional Description ................................................................
KSZ8081MNX/RNB 1.0 INTRODUCTION 1.1 General Description The KSZ8081 is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. The KSZ8081 is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core.
KSZ8081MNX/RNB PIN DESCRIPTION AND CONFIGURATION KSZ8081MNX 32-QFN PIN ASSIGNMENT (TOP VIEW) RST# LED1/SPEED LED0/NWAYEN CRS/CONFIG1 COL/CONFIG0 TXD3 TXD2 FIGURE 2-1: TXD1 2.0 32 31 30 29 28 27 26 25 GND VDD_1.2 VDDA_3.
KSZ8081MNX/RNB TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX (CONTINUED) Pin Number Name Buffer Type (Note 2-1) 8 XO O Crystal feedback for 25 MHz crystal. This pin is a no connect if an oscillator or external clock source is used. 9 XI I Crystal / Oscillator / External Clock Input. 25 MHz ±50 ppm. 10 REXT I Set PHY transmit output current. Connect a 6.49 kΩ resistor to ground on this pin.
KSZ8081MNX/RNB TABLE 2-1: Pin Number PIN DESCRIPTION — KSZ8081MNX (CONTINUED) Name Buffer Type (Note 2-1) Description Ipu/Opu Interrupt Output: Programmable Interrupt Output. This pin has a weak pull-up, is open-drain, and requires an external 1.0 kΩ pull-up resistor. Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-assertion of reset. See the section Strap-In Options – KSZ8081MNX for details. INTRP/ 21 NAND_Tree# MII Mode: MII Transmit Clock Output.
KSZ8081MNX/RNB TABLE 2-1: PIN DESCRIPTION — KSZ8081MNX (CONTINUED) Pin Number Name Buffer Type (Note 2-1) Description LED Output: Programmable LED1 Output. Config Mode: Latched as Speed (Register 0h, Bit [13]) at the deassertion of reset. See the Strap-In Options – KSZ8081MNX section for details.
KSZ8081MNX/RNB 2.1 Strap-In Options – KSZ8081MNX The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7 kΩ) or pull-downs (1.0 kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.
KSZ8081MNX/RNB TXD1 KSZ8081RNB 32-QFN PIN ASSIGNMENT (TOP VIEW) RST# LED1/SPEED LED0/NWAYEN CONFIG1 CONFIG0 NC NC FIGURE 2-2: 32 31 30 29 28 27 26 25 GND VDD_1.2 VDDA_3.
KSZ8081MNX/RNB TABLE 2-3: Pin Number 14 15 PIN DESCRIPTION — KSZ8081RNB (CONTINUED) Pin Name PHYAD1 RXD1/ PHYAD2 Type (Note 2-1) Pin Function Ipd/O The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset. See the Strap-in Options – KSZ8081RNB section for details. Ipd/O RMII Mode: RMII Receive Data Output[1] (Note 2-2). Config Mode: The pull-up/pull-down value is latched as PHYADDR[2] at the de-assertion of reset. See the Strap-in Options – KSZ8081RNB section for details.
KSZ8081MNX/RNB TABLE 2-3: PIN DESCRIPTION — KSZ8081RNB (CONTINUED) Pin Number Pin Name Type (Note 2-1) Pin Function 28 CONFIG0 Ipd/O The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See the Strap-in Options – KSZ8081RNB section for details. 29 CONFIG1 Ipd/O The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See the Strap-in Options – KSZ8081RNB section for details. LED Output: Programmable LED0 Output.
KSZ8081MNX/RNB = Input with internal pull-up (see Electrical Characteristics for value) and output with internal pull-up (see Electrical Characteristics for value). NC = Pin is not bonded to the die. Note 2-2 RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the MAC. Note 2-3 RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock.
KSZ8081MNX/RNB TABLE 2-4: Pin Number 19 21 Note 2-1 STRAP-IN OPTIONS (CONTINUED) Pin Name Type (Note 2-1) B-CAST_OFF Ipd/O NAND_Tree# Ipu/ Opu Pin Function Broadcast off – for PHY Address 0 Pull-up = PHY Address 0 is set as an unique PHY address Pull-down (default) = PHY Address 0 is set as a broadcast PHY address At the de-assertion of reset, this pin value is latched by the chip.
KSZ8081MNX/RNB 3.0 FUNCTIONAL DESCRIPTION 3.1 10BASE-T/100BASE-TX Transceiver The KSZ8081 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.
KSZ8081MNX/RNB 3.1.5 10BASE-T RECEIVE On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder.
KSZ8081MNX/RNB FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.2 MII Interface (KSZ8081MNX Only) The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification.
KSZ8081MNX/RNB 3.2.1 MII SIGNAL DEFINITION Table 3-1 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information. TABLE 3-1: MII SIGNAL DEFINITION MII Signal Name TXC Direction (with respect to PHY, Direction KSZ8081MNX (with respect to MAC) signal) Description Transmit Clock (2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps) Output Input TXEN Input Output Transmit Enable TXD[3:0] Input Output Transmit Data[3:0] RXC Output Input Receive Clock (2.
KSZ8081MNX/RNB 3.2.7 RECEIVE DATA[3:0] (RXD[3:0]) RXD[3:0] transitions synchronously with respect to RXC. For each clock period in which RXDV is asserted, RXD[3:0] transfers a nibble of recovered data from the PHY. 3.2.8 RECEIVE ERROR (RXER) RXER is asserted for one or more RXC periods to indicate that a symbol error (for example, a coding error that a PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being transferred from the PHY.
KSZ8081MNX/RNB 3.3 RMII Data Interface (KSZ8081RNB Only) The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: • Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference clock). • 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.
KSZ8081MNX/RNB 3.3.5 TRANSMIT ENABLE (TXEN) TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated before the first REF_CLK following the final dibit of a frame. TXEN transitions synchronously with respect to REF_CLK. 3.3.6 TRANSMIT DATA[1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK.
KSZ8081MNX/RNB FIGURE 3-3: KSZ8081RNB RMII INTERFACE (25 MHZ CLOCK MODE) RMII MAC KSZ8081RNB CRS_DV CRS_DV RXD[1:0] RXD[1:0] RXER RX_ER TXEN TX_EN TXD[1:0] TXD[1:0] REF_CLK REF_CLK XI XO 25MHz XTAL 22pF FIGURE 3-4: 22pF KSZ8081RNB RMII INTERFACE (50 MHZ CLOCK MODE) RMII MAC KSZ8081RNB CRS_DV CRS_DV RXD[1:0] RXD[1:0] RXER RX_ER TXEN TX_EN TXD[1:0] TXD[1:0] REF_CLK XI 50MHz OSC DS00002202C-page 22 2016-2018 Microchip Technology Inc.
KSZ8081MNX/RNB 3.4 Back-to-Back Mode – 100 Mbps Copper Repeater Two KSZ8081MNX/RNB devices can be connected back-to-back to form a 100BASE-TX copper repeater. FIGURE 3-5: KSZ8081MNX/RNB TO KSZ8081MNX/RNB BACK-TO-BACK COPPER REPEATER RxD RXP/RXM TXP/TXM KSZ8081MNX/RNB (COPPER MODE) TxD 25MHz/ 50MHz XI OSC XI TXP/TXM KSZ8081MNX/RNB (COPPER MODE) RxD RXP/RXM 3.4.
KSZ8081MNX/RNB 3.5 MII Management (MIIM) Interface The KSZ8081MNX/RNB supports the IEEE 802.3 MII management interface, also known as the Management Data Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and control the state of the KSZ8081MNX/RNB. An external device with MIIM capability is used to read the PHY status and/ or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.
KSZ8081MNX/RNB TABLE 3-5: MDI/MDI-X PIN DEFINITION MDI 3.7.1 MDI-X RJ-45 Pin Signal RJ-45 Pin Signal 1 TX+ 1 RX+ 2 TX– 2 RX– 3 RX+ 3 TX+ 6 RX– 6 TX– STRAIGHT CABLE A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-6 shows a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).
KSZ8081MNX/RNB FIGURE 3-7: TYPICAL CROSSOVER CABLE CONNECTION 10/100 ETHERNET MEDIA DEPENDENT INTERFACE 1 RECEIVE PAIR 10/100 ETHERNET MEDIA DEPENDENT INTERFACE CROSSOVER CABLE 1 RECEIVE PAIR 2 2 3 3 4 4 5 5 6 6 7 7 8 8 TRANSMIT PAIR TRANSMIT PAIR MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) 3.8 MODULAR CONNECTOR (RJ-45) HUB (REPEATER OR SWITCH) Loopback Mode The KSZ8081MNX/RNB supports the following loopback operations to verify analog and/or digital data paths.
KSZ8081MNX/RNB The following programming action and register settings are used for local loopback mode. For 10 Mbps/100 Mbps loopback, •Set Register 0h, Bit [14] = 1 // Enable local loopback mode Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed Bit [12] = 0 // Disable auto-negotiation Bit [8] = 1 // Select full-duplex mode The following steps should be applied if unwanted frames appear outside the copper port in the local feedback. 1. 2. 3. Set register 1Fh bit [3] to ‘1’ to disable the transmitter.
KSZ8081MNX/RNB LinkMD® Cable Diagnostic 3.9 The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault.
KSZ8081MNX/RNB TABLE 3-6: Pin Number Pin Name NAND Tree Description 11 MDIO Input 12 MDC Input 15 RXD1 Input 16 RXD0 Input 18 CRS_DV Input 19 REF_CLK Input 21 INTRP Input 23 TXEN Input 30 LED0 Input 24 TXD0 Input 25 TXD1 Output KS8081MNX supports partial NAND tree test pins. Table 3-6 lists partial NAND tree test pins. If full NAND tree testing is required, please use KSZ8091MNX device that supports all the required pins. Note 3-1 TABLE 3-7: 3.10.
KSZ8081MNX/RNB Each KSZ8081MNX/RNB NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8081MNX/RNB input pin toggles from high to low, the input pin has a fault. 3.11 Power Management The KSZ8081MNX/RNB incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections. 3.11.
KSZ8081MNX/RNB 3.12 Reference Circuit for Power and Ground Connections The KSZ8081MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground connections are shown in Figure 3-10 and Table 3-8 for 3.3V VDDIO. FIGURE 3-10: KSZ8081MNX/RNB POWER AND GROUND CONNECTIONS 2 VDD_1.2 FERRITE BEAD 3 22μF 2.2μF 0.1μF VDDA_3.3 0.1μF KSZ8081MNX/RNB 3.3V 17 22μF VDDIO 0.
KSZ8081MNX/RNB 3.13 Typical Current/Power Consumption Table 3-9, Table 3-10 ,and Table 3-11 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081MNX/RNB device for the indicated nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator current for the 1.2V core. 3.13.1 TRANSCEIVER (3.3V), DIGITAL I/OS (3.
KSZ8081MNX/RNB 3.13.3 TRANSCEIVER (3.3V), DIGITAL I/OS (1.8V) TABLE 3-11: TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V) 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) Total Chip Power mA mA mW 100BASE-TX Link-up (no traffic) 34 11 132 100BASE-TX Full-duplex @ 100% utilization 34 12 134 10BASE-T Link-up (no traffic) 15 9.0 65.7 10BASE-T Full-duplex @ 100% utilization 27 9.0 105 Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 9.0 65.7 EDPD mode (Reg.
KSZ8081MNX/RNB 4.0 REGISTER DESCRIPTIONS 4.
KSZ8081MNX/RNB 4.2 Register Description TABLE 4-2: Address REGISTER DESCRIPTION Name Description Mode Default RW/SC 0 RW 0 RW Set by the SPEED strapping pin. See the Strap-In Options – KSZ8081MNX section for details. RW Set by the NWAYEN strapping pin. See the Strap-In Options – KSZ8081MNX section for details. RW 0 RW Set by the ISO strapping pin. See the Strap-In Options – KSZ8081MNX section for details. RW/SC 0 RW The inverse of the DUPLEX strapping pin value.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Mode Default RW/SC 0 1 = Loopback mode 0 = Normal operation RW 0 1 = 100 Mbps 0 = 10 Mbps Speed Select This bit is ignored if auto-negotiation is enabled (Register 0.12 = 1). RW Set by the SPEED strapping pin. See the Strap-In Options – KSZ8081MNX section for details. 0.15 Reset 0.14 Loopback 0.13 Description 1 = Software reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Description Mode Default 10BASE-T Half-Duplex 1 = Capable of 10 Mbps half-duplex 0 = Not capable of 10 Mbps halfduplex RO 1 Reserved Reserved RO 000_0 1.6 No Preamble 1 = Preamble suppression 0 = Normal preamble RO 1 1.5 Auto-Negotiation Complete 1 = Auto-negotiation process completed 0 = Auto-negotiation process not completed RO 0 1.4 Remote Fault 1 = Remote fault 0 = No remote fault RO/LH 0 1.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Description Mode Default 4.8 1 = 100 Mbps full-duplex capable 100BASE-TX 0 = No 100 Mbps full-duplex Full-Duplex capability RW Set by the SPEED strapping pin. See the Strap-In Options – KSZ8081MNX section for details. 4.7 1 = 100 Mbps half-duplex capable 100BASE-TX 0 = No 100 Mbps half-duplex Half-Duplex capability RW Set by the SPEED strapping pin. See the Strap-In Options – KSZ8081MNX section for details. 4.
KSZ8081MNX/RNB TABLE 4-2: REGISTER DESCRIPTION (CONTINUED) Address Name Description Mode Default 6.2 Next Page Able 1 = Local device has next page capability 0 = Local device does not have next page capability RO 1 6.1 Page Received 1 = New page received 0 = New page not received yet RO/LH 0 RO 0 6.0 1 = Link partner has auto-negotiation Link Partner capability Auto-Negotia0 = Link partner does not have autotion Able negotiation capability Register 7h – Auto-Negotiation Next Page 7.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Description Mode Default 11.5 Slow-Oscillator Mode Enable Slow-oscillator mode is used to disconnect the input reference crystal/clock on the XI pin and select the on-chip slow oscillator when the KSZ8081MNX/RNB device is not in use after power-up. 1 = Enable 0 = Disable This bit automatically sets software power-down to the analog side when enabled. RW 0 11.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Description Mode Default [000] = Strap to PHY Address 0 [001] = Strap to PHY Address 1 [010] = Strap to PHY Address 2 PHYAD[2:0] [011] = Strap to PHY Address 3 17.15:13 Strap-In Status [100] = Strap to PHY Address 4 [101] = Strap to PHY Address 5 [110] = Strap to PHY Address 6 [111] = Strap to PHY Address 7 RO — 17.12:10 RO — RO — RO — Register 17h – Operation Mode Strap Status 17.9 17.
KSZ8081MNX/RNB TABLE 4-2: REGISTER DESCRIPTION (CONTINUED) Address Name 18.5:0 Reserved Description Mode Default RO 00_0001 RW 0 RW 0 RW 0 1B.12 1 = Enable parallel detect fault interParallel Detect rupt Fault Interrupt 0 = Disable parallel detect fault interEnable rupt RW 0 1B.11 Link Partner Acknowledge Interrupt Enable 1 = Enable link partner acknowledge interrupt 0 = Disable link partner acknowledge interrupt RW 0 1B.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Description Mode Default RW/SC 0 Register 1Dh – LinkMD Control/Status Cable Diagnostic Test Enable 1 = Enable cable diagnostic test. After test has completed, this bit is self-cleared. 0 = Indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. 1D.
KSZ8081MNX/RNB TABLE 4-2: Address REGISTER DESCRIPTION (CONTINUED) Name Description Mode Default Register 1Fh – PHY Control 2 HP_MDIX 1 = HP Auto MDI/MDI-X mode 0 = Auto MDI/MDI-X mode RW 1 1F.14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 1 = MDI-X mode Transmit on RXP,RXM (pins 5, 4) andReceive on TXP,TXM (pins 7, 6) 0 = MDI mode Transmit on TXP,TXM (pins 7, 6) and Receive on RXP,RXM (pins 5, 4) RW 0 1F.
KSZ8081MNX/RNB 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VIN) (VDD_1.2).................................................................................................................................................... –0.5V to +1.8V (VDDIO, VDDA_3.3) ...................................................................................................................................... –0.5V to +5.0V Input Voltage (all inputs) ........................................
KSZ8081MNX/RNB 6.0 ELECTRICAL CHARACTERISTICS Symbol Parameter Condition Min. Typ. Max. Units Supply Current (VDDIO, VDDA_3.3 = 3.3V) IDD1_3.3V 10BASE-T Full-duplex traffic @ 100% utilization — 41 — mA IDD2_3.3V 100BASE-TX Full-duplex traffic @ 100% utilization — 47 — mA IDD3_3.3V EDPD Mode Ethernet cable disconnected (reg. 18h.11 = 0) — 20 — mA IDD4_3.3V Power-Down Mode Software power-down (reg. 0h.11 = 1) — 4 — mA VDDIO = 3.3V 2.0 — — VDDIO = 2.5V 1.
KSZ8081MNX/RNB Symbol Parameter Condition Min. Typ. Max. Units 10BASE-T Transmit (measured differentially after 1:1 transformer) VP tr, tf Peak Differential Output Voltage 100Ω termination across differential output 2.2 — 2.8 V Jitter Added Peak-to-peak — — 3.5 ns Rise/Fall Time — — 25 — ns 5 MHz square wave — 400 — mV R(ISET) = 6.49 kΩ — 0.65 — V Peak-to-peak.
KSZ8081MNX/RNB 7.0 TIMING DIAGRAMS 7.1 MII SQE Timing (10BASE-T) FIGURE 7-1: MII SQE TIMING (10BASE-T) tWL TXC tWH tP TXEN tSQE COL TABLE 7-1: tSQEP MII SQE TIMING (10BASE-T) PARAMETERS Timing Parameters Description Min. Typ. Max. Units tP TXC period 200 — — ns TXC pulse width low — — 400 tWL tWH TXC pulse width high — 200 — ns tSQE COL (SQE) delay after TXEN de-asserted — 2.2 — µs tSQEP COL (SQE) pulse duration — 1.0 — µs 7.
KSZ8081MNX/RNB TABLE 7-2: MII TRANSMIT TIMING (10BASE-T) PARAMETERS (CONTINUED) Timing Parameters Description Min. Typ. Max. Units tHD1 TXD[3:0] hold from rising edge of TXC 0 — — ns tHD2 TXEN hold from rising edge of TXC 0 — — ns tCRS1 TXEN high to CRS asserted latency 600 — ns tCRS2 TXEN low to CRS de-asserted latency 1.0 — µs 7.
KSZ8081MNX/RNB 7.4 MII Transmit Timing (BASE100BASE-TX) FIGURE 7-4: MII TRANSMIT TIMING (BASE100BASE-TX) tWL TXC tSU2 TXEN tSU1 TXD[3:0] tWH tHD2 tP tHD1 DATA IN tCRS2 tCRS1 CRS TABLE 7-4: MII TRANSMIT TIMING (BASE100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ. Max.
KSZ8081MNX/RNB TABLE 7-5: MII RECEIVE TIMING (BASE100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ. Max. Units 40 ns tP RXC period tWL RXC pulse width low — — 20 — — tWH RXC pulse width high — 20 — ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 16 21 25 ns tFLAT CRS to (RXDV, RXD[3:0] latency — 170 — ns 7.
KSZ8081MNX/RNB TABLE 7-6: RMII TIMING PARAMETERS – KSZ8081RNB (25 MHZ INPUT TO XI PIN, 50 MHZ OUTPUT FROM REF_CLK PIN) Timing Parameter Description Min. Typ. Max Units tCYC Clock cycle — 20 — ns t1 Setup time 4 — — ns t2 Hold time 2 — — ns tOD Output delay 7 10 13 ns TABLE 7-7: RMII TIMING PARAMETERS – KSZ8081RNB (25 MHZ INPUT TO XI PIN) Timing Parameter Description Min. Typ.
KSZ8081MNX/RNB TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS Timing Parameter Description Min. Typ. Max. Units 16 24 ms tBTB FLP burst to FLP burst 8 tFLPW FLP burst width — 2 — ms tPW Clock/Data pulse width — 100 — ns tCTD Clock pulse to data pulse 55.5 64 69.5 µs tCTC Clock pulse to clock pulse 111 128 139 µs — Number of clock/data pulses per FLP burst 17 — 33 — 7.
KSZ8081MNX/RNB 7.9 Power-up/Reset Timing The KSZ8081MNX/RNB reset timing requirement is summarized in Figure 7-10 and Table 7-10. FIGURE 7-10: POWER-UP/RESET TIMING SUPPLY VOLTAGES tVR tSR RST# tCS tCH STRAP-IN VALUE tRC STRAP-IN / OUTPUT PIN TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS Parameter Description Min. Max. Units tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 — µs tSR Stable supply voltage (VDDIO, VDDA_3.
KSZ8081MNX/RNB 7.10 Reset Circuit Figure 7-11 shows a reset circuit recommended for powering up the KSZ8081MNX/RNB if reset is triggered by the power supply. FIGURE 7-11: RECOMMENDED RESET CIRCUIT VDDIO D1: 1N4148 D1 KSZ8081MNX/RNB R 10K RST# C 10μF Figure 7-12 Shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset.
KSZ8081MNX/RNB 7.11 Reference Circuits – LED Strap-In Pins The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strapping pins are shown in Figure 7-13 for 3.3V and 2.5V VDDIO. FIGURE 7-13: REFERENCE CIRCUITS FOR LED STRAPPING PINS VDDIO = 3.3V, 2.5V PULL_UP 4.7kΩ 220Ω KSZ8081MNX/RXB LED PIN VDDIO = 3.3V, 2.5V FLOAT 220Ω KSZ8081MNX/RXB LED PIN VDDIO = 3.3V, 2.5V PULL-DOWN 220Ω KSZ8081MNX/RXB LED PIN 1kΩ For using 1.8V VDDIO, should select parts with low 1.
KSZ8081MNX/RNB 7.12 Reference Clock – Connection and Selection A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081MNX/ RNB. For the KSZ8081MNX in all operating modes and for the KSZ8081RNB in RMII – 25 MHz Clock Mode, the reference clock is 25 MHz. The reference clock connections to XI (Pin 9) and XO (Pin 8), and the reference clock selection criteria, are provided in Figure 7-14 and Table 7-11.
KSZ8081MNX/RNB 7.13 Magnetic – Connection and Selection The KSZ8081MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs.
KSZ8081MNX/RNB Table 7-14 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that can be used with the KSZ8081MNX/RNB.
KSZ8081MNX/RNB 8.0 PACKAGE OUTLINE FIGURE 8-1: DS00002202C-page 60 32-LEAD QFN 5 MM × 5 MM PACKAGE AND RECOMMENDED PCB LAND PATTERN 2016-2018 Microchip Technology Inc.
KSZ8081MNX/RNB APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry DS000002202C (01-09-18) Table 4-2, "Register Description" Updates to the following addresses: 4.15, 5.4:0, 7.15, 18.5:0 and 1E.3 Table 3-9, "Typical Current/ Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 3.3V)" and Table 3-10, "Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 2.5V)" Values for “Total Chip Power” modified.
KSZ8081MNX/RNB THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ8081MNX/RNB PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
KSZ8081MNX/RNB Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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