Datasheet

Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 63
Revision 1.4
Reset Circuit
Figure 21 shows a reset circuit recommended for powering up the KSZ8081MNX/RNB if reset is triggered by the power
supply.
Figure 21. Recommended Reset Circuit
Figure 22 Shows a reset circuit recommended for applications where reset is driven by another device (for example, the
CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2 is used
if using different VDDIO between the switch and CPU/FPGA, otherwise, the different VDDIO will fight each other. If
different VDDIO have to use in a special case, a low VF (<0.3V) diode is required (For example, VISHAY’s BAT54,
MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same VDDIO
voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same
VDDIO voltage.
CPU/FPGA
VDDIO
C 10uF
R 10K
RST
RST_OUT_n
D1
D2
KSZ8081MNX/RNB
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output