Datasheet

Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 6
Revision 1.4
List of Figures
Figure 1. Auto-Negotiation Flow Chart .................................................................................................................................. 21
Figure 2. KSZ8081MNX MII Interface ................................................................................................................................... 24
Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode) .............................................................................................. 27
Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode) .............................................................................................. 27
Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Back-to-Back Copper Repeater ....................................................... 28
Figure 6. Typical Straight Cable Connection ........................................................................................................................ 31
Figure 7. Typical Crossover Cable Connection .................................................................................................................... 31
Figure 8. Local (Digital) Loopback ........................................................................................................................................ 32
Figure 9. Remote (Analog) Loopback ................................................................................................................................... 33
Figure 10. KSZ8081MNX/RNB Power and Ground Connections ......................................................................................... 38
Figure 11. MII SQE Timing (10Base-T) ................................................................................................................................ 54
Figure 12. MII Transmit Timing (10Base-T) .......................................................................................................................... 55
Figure 13. MII Receive Timing (10Base-T) ........................................................................................................................... 56
Figure 14. MII Transmit Timing (100Base-TX) ...................................................................................................................... 57
Figure 15. MII Receive Timing (100Base-TX) ....................................................................................................................... 58
Figure 16. RMII Timing – Data Received from RMII ............................................................................................................. 59
Figure 17. RMII Timing – Data Input to RMII ........................................................................................................................ 59
Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing .................................................................................................. 60
Figure 19. MDC/MDIO Timing ............................................................................................................................................... 61
Figure 20. Power-up/Reset Timing ....................................................................................................................................... 62
Figure 21. Recommended Reset Circuit ............................................................................................................................... 63
Figure 22. Recommended Reset Circuit for Interfacing with CPU/FPGA Reset Output ...................................................... 63
Figure 23. Reference Circuits for LED Strapping Pins ......................................................................................................... 64
Figure 24. 25MHz Crystal/Oscillator Reference Clock Connection ...................................................................................... 65
Figure 25. 50MHz Oscillator Reference Clock Connection .................................................................................................. 65
Figure 26. Typical Magnetic Interface Circuit ........................................................................................................................ 66