Datasheet

Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 51
Revision 1.4
Register Description (Continued)
Address Name Description Mode
(10)
Default
Register 1Fh – PHY Control 2
1F.11 Force Link
1 = Force link pass
0 = Normal link operation
This bit bypasses the control logic and allows
the transmitter to send a pattern even if there is
no link.
RW 0
1F.10 Power Saving
1 = Enable power saving
0 = Disable power saving
RW 0
1F.9 Interrupt Level
1 = Interrupt pin active high
0 = Interrupt pin active low
RW 0
1F.8 Enable Jabber
1 = Enable jabber counter
0 = Disable jabber counter
RW 1
1F.7
RMII
Reference
Clock Select
1 = RMII 50MHz clock mode; clock input to XI
(Pin 9) is 50MHz
0 = RMII 25MHz clock mode; clock input to XI
(Pin 9) is 25MHz
This bit applies only to KSZ8081RNB.
RW 0
1F.6 Reserved Reserved RW 0
1F.5:4 LED Mode
[00] = LED1: Speed
LED0: Link/Activity
[01] = LED1: Activity
LED0: Link
[10], [11] = Reserved
RW 00
1F.3
Disable
Transmitter
1 = Disable transmitter
0 = Enable transmitter
RW 0
1F.2
Remote
Loopback
1 = Remote (analog) loopback is enabled
0 = Normal mode
RW 0
1F.1
Enable SQE
Test
1 = Enable SQE test
0 = Disable SQE test
RW 0
1F.0
Disable Data
Scrambling
1 = Disable scrambler
0 = Enable scrambler
RW 0