Datasheet

Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 35
Revision 1.4
NAND Tree Support
The KSZ8081MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The
NAND tree is a chain of nested NAND gates in which each KSZ8081MNX/RNB digital I/O (NAND tree input) pin is an
input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND
gates.
The NAND tree test process includes:
• Enabling NAND tree mode
• Pulling all NAND tree input pins high
• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order
• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input
driven low
Table 7 and Table 8 list the NAND tree pin orders for KSZ8081MNX and KSZ8081RNB, respectively.
Table 7. NAND Tree Test Pin Order for KSZ8081MNX
Pin Number Pin Name NAND Tree Description
11 MDIO Input
12 MDC Input
15 RXD1 Input
16 RXD0 Input
18 CRS_DV Input
19 REF_CLK Input
21 INTRP Input
23 TXEN Input
30 LED0 Input
24 TXD0 Input
25 TXD1 Output
Note: KS8081MNX supports partial NAND tree test pins. Table 7 lists partial NAND tree test pins. If full NAND tree testing
is required, please use KSZ8091MNX device that supports all the required pins.