Datasheet
Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 16
Revision 1.4
Pin Description – KSZ8081RNB (Continued)
Pin Number Pin Name Type
(6)
Pin Function
17 VDDIO P 3.3V, 2.5V, or 1.8V digital V
DD
.
18
CRS_DV/
CONFIG2
Ipd/O
RMII Mode: RMII Carrier Sense/Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset.
See the Strapping Options – KSZ8081RNB section for details.
19
REF_CLK/
B-CAST_OFF
Ipd/O
RMII Mode: 25MHz Mode. This pin provides the 50MHz RMII reference clock output
to the MAC. See also XI (Pin 9).
50MHz mode: This pin is a no connect. See also XI (Pin 9).
Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB section for details.
20
RXER/
ISO
Ipd/O
RMII Mode: RMII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset.
See the Strapping Options – KSZ8081RNB section for details.
21
INTRP/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up
resistor.
Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset.
See the Strapping Options – KSZ8081RNB section for details.
22 NC - No Connect. This pin is not bonded and can be left floating.
23 TXEN I RMII Transmit Enable input.
24 TXD0 I
RMII Transmit Data Input[0]
(
8
)
.
25 TXD1 I
RMII Transmit Data Input[1]
(
8
)
.
26 NC - No Connect. This pin is not bonded and can be left floating.
27 NC - No Connect. This pin is not bonded and can be left floating.
28 CONFIG0 Ipd/O
The pull-up/pull-down value is latched as CONFIG0 at the de-assertion of reset. See
the Strapping Options – KSZ8081RNB section for details.
29 CONFIG1 Ipd/O
The pull-up/pull-down value is latched as CONFIG1 at the de-assertion of reset. See
the Strapping Options – KSZ8081RNB section for details.
Note:
8. RMII TX Mode: The TXD[1:0] bits are synchronous with the 50MHz RMII Reference Clock. For each clock period in which TXEN is asserted, two bits
of data are received by the PHY from the MAC.