Datasheet

Micrel, Inc.
KSZ8081MNX/KSZ8081RNB
August
19, 2015 10
Revision 1.4
Pin Description – KSZ8081MNX (Continued)
Pin Number Pin Name Type
(2)
Pin Function
16
RXD0/
DUPLEX
Ipu/O
MII Mode: MII Receive Data Output[0]
(
3
)
.
Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for details.
17 VDDIO P 3.3V, 2.5V, or 1.8V digital V
DD
18
RXDV/
CONFIG2
Ipd/O
MII Mode: MII Receive Data Valid Output.
Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for details.
19
RXC/
B-CAST_OFF
Ipd/O
MII Mode: MII Receive Clock Output.
Config Mode: The pull-up/pull-down value is latched as B-CAST_OFF at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for details.
20
RXER/
ISO
Ipd/O
MII mode: MII Receive Error Output.
Config Mode: The pull-up/pull-down value is latched as ISOLATE at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for details.
21
INTRP/
NAND_Tree#
Ipu/Opu
Interrupt Output: Programmable Interrupt Output.
This pin has a weak pull-up, is open-drain, and requires an external 1.0kΩ pull-up
resistor.
Config Mode: The pull-up/pull-down value is latched as NAND Tree# at the de-
assertion of reset.
See the Strapping Options – KSZ8081MNX section for details
22 TXC Ipd/O
MII Mode: MII Transmit Clock Output.
At the de-assertion of reset, this pin needs to latch in a pull-down value for normal
operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for solution. It is
better having an external pull-down resistor to avoid MAC side pulls this pin high.
23 TXEN I MII Mode: MII Transmit Enable input.
24 TXD0 I MII Mode: MII Transmit Data Input[0]
(4)
.
25 TXD1 I MII Mode: MII Transmit Data Input[1]
(4)
.
26 TXD2 I MII Mode: MII Transmit Data Input[2]
(4)
.
27 TXD3 I MII Mode: MII Transmit Data Input[3]
(4)
.
28
COL/
CONFIG0
Ipd/O
MII Mode: MII Collision Detect output.
Config Mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for details.
29
CRS/
CONFIG1
Ipd/O
MII mode: MII Carrier Sense output
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset.
See the Strapping Options – KSZ8081MNX section for details.
Note:
4. MII TX Mode: The TXD[3:0] bits are synchronous with TXC. When TXEN is asserted, TXD[3:0] presents valid data from the MAC. TXD[3:0] has no
effect on the PHY when TXEN is de-asserted.