Datasheet

ManualsBrandsMicrochip ManualsIntegrated Circuits (ICs)BASE-TX Physical Layer Transceiver Ethernet/MII/PHY QFN 47mA

KSZ8081MNX/KSZ8081RNB

10Base-T/100Base-TX

Physical Layer Transceiver

Revision 1.4

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

August

19, 2015

Revision 1.4

General Description

The KSZ8081 is a single-supply 10Base-T/100Base-TX

Ethernet physical-layer transceiver for transmission and

reception of data over standard CAT-5 unshielded twisted

pair (UTP) cable.

The KSZ8081 is a highly-integrated PHY solution. It

reduces board cost and simplifies board layout by using

on-chip termination resistors for the differential pairs and

by integrating a low-noise regulator to supply the 1.2V

core.

The KSZ8081MNX offers the Media Independent Interface

(MII) and the KSZ8081RNB offers the Reduced Media

Independent Interface (RMII) for direct connection with

MII/RMII-compliant Ethernet MAC processors and

switches.

A 25MHz crystal is used to generate all required clocks,

including the 50MHz RMII reference clock output for the

KSZ8081RNB.

The KSZ8081 provides diagnostic features to facilitate

system bring-up and debugging in production testing and

in product deployment. Parametric NAND tree support

enables fault detection between KSZ8081 I/Os and the

board. Micrel LinkMD

TDR-based cable diagnostics

identify faulty copper cabling.

The KSZ8081MNX and KSZ8081RNB are available in 32-

pin, lead-free QFN packages (see “Ordering Information”).

Datasheets and support documentation are available on

website at: www.micrel.com

Features

• Single-chip 10Base-T/100Base-TX IEEE 802.3

compliant Ethernet transceiver

• MII interface support (KSZ8081MNX)

• RMII v1.2 Interface support with a 50MHz reference

clock output to MAC, and an option to input a 50MHz

reference clock (KSZ8081RNB)

• Back-to-back mode support for a 100Mbps copper

repeater

• MDC/MDIO management interface for PHY register

configuration

• Programmable interrupt output

• LED outputs for link, activity, and speed status indication

• On-chip termination resistors for the differential pairs

• Baseline wander correction

• HP Auto MDI/MDI-X to reliably detect and correct

straight-through and crossover cable connections with

disable and enable option

• Auto-negotiation to automatically select the highest link-

up speed (10/100Mbps) and duplex (half/full)

• Power-down and power-saving modes

• LinkMD TDR-based cable diagnostics to identify faulty

copper cabling

• Parametric NAND Tree support for fault detection

between chip I/Os and the board

• HBM ESD rating (6kV)

Functional Diagram

Summary of content (69 pages)

PAGE 1
KSZ8081MNX/KSZ8081RNB 10Base-T/100Base-TX Physical Layer Transceiver Revision 1.4 General Description Features The KSZ8081 is a single-supply 10Base-T/100Base-TX Ethernet physical-layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable. • Single-chip 10Base-T/100Base-TX IEEE 802.3 compliant Ethernet transceiver • MII interface support (KSZ8081MNX) • RMII v1.
PAGE 2
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Features (Continued) Applications • Loopback modes for diagnostics • Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V • Built-in 1.2V regulator for core • Available in 32-pin (5mm × 5mm) QFN package • • • • • • Game console IP phone IP set-top box IP TV LOM Printer Description Ordering Information Temperature Range Package Lead Finish 0°C to +70°C 32-Pin QFN Pb-Free MII, Commercial Temperature.
PAGE 3
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Revision History Revision 1.0 Date 11/5/12 Summary of Changes Initial release of datasheet. Removed copper wire bonding part numbers from Ordering Information. Added note for TXC (Pin 22) and Register 16h, Bit [15] regarding a Reserved Factory Mode for KSZ8081MNX device. 1.1 2/6/14 Corrected TXC (Pin 22) pin type for KSZ8081MNX device. Removed TXC and RXC clock connections for MII Back-to-Back mode. This is a datasheet correction. There is no change to the silicon.
PAGE 4
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Table of Contents List of Figures .......................................................................................................................................................................... 6 List of Tables ........................................................................................................................................................................... 7 Pin Configuration – KSZ8081MNX ................................................
PAGE 5
Micrel, Inc. KSZ8081MNX/KSZ8081RNB NAND Tree Support .............................................................................................................................................................. 35 NAND Tree I/O Testing ..................................................................................................................................................... 36 Power Management .......................................................................................................
PAGE 6
Micrel, Inc. KSZ8081MNX/KSZ8081RNB List of Figures Figure 1. Auto-Negotiation Flow Chart .................................................................................................................................. 21 Figure 2. KSZ8081MNX MII Interface ................................................................................................................................... 24 Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode) ..............................................................
PAGE 7
Micrel, Inc. KSZ8081MNX/KSZ8081RNB List of Tables Table 1. MII Signal Definition ................................................................................................................................................ 22 Table 2. RMII Signal Defintion .............................................................................................................................................. 25 Table 3. MII Signal Connection for MII Back-to-Back Mode (100Base-TX Copper Repeater) ..................
PAGE 8
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Configuration – KSZ8081MNX 32-Pin 5mm × 5mm QFN August 19, 2015 8 Revision 1.
PAGE 9
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081MNX Type (2) Pin Number Pin Name Pin Function 1 GND GND 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8081MNX). Decouple with 2.2µF and 0.1µF capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD. 4 RXM I/O Physical receive or transmit signal (− differential). 5 RXP I/O Physical receive or transmit signal (+ differential). 6 TXM I/O Physical transmit or receive signal (− differential).
PAGE 10
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081MNX (Continued) Pin Number Pin Name Type (2) Pin Function (3 ) MII Mode: MII Receive Data Output[0] . 16 RXD0/ DUPLEX Ipu/O Config Mode: The pull-up/pull-down value is latched as DUPLEX at the de-assertion of reset. See the Strapping Options – KSZ8081MNX section for details. 17 VDDIO P 3.3V, 2.5V, or 1.8V digital VDD MII Mode: MII Receive Data Valid Output.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081MNX (Continued) Pin Number Pin Name Type (2) Pin Function LED Output: Programmable LED0 output. Config Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at the deassertion of reset. See the Strapping Options – KSZ8081MNX section for details.
PAGE 12
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Strapping Options – KSZ8081MNX The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC MII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.
PAGE 13
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Strapping Options – KSZ8081MNX (Continued) Pin Number Pin Name Type (5 ) Pin Function Nway Auto-Negotiation Enable: 30 NWAYEN Ipu/O Pull-up (default) = Enable auto-negotiation Pull-down = Disable auto-negotiation At the de-assertion of reset, this pin value is latched into Register 0h, Bit [12].
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Configuration – KSZ8081RNB 32-Pin 5mm × 5mm QFN August 19, 2015 14 Revision 1.
PAGE 15
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081RNB Type (6) Pin Number Pin Name Pin Function 1 GND GND 2 VDD_1.2 P 1.2V core VDD (power supplied by KSZ8081RNB). Decouple with 2.2µF and 0.1µF capacitors to ground. 3 VDDA_3.3 P 3.3V analog VDD. 4 RXM I/O Physical receive or transmit signal (− differential). 5 RXP I/O Physical receive or transmit signal (+ differential). 6 TXM I/O Physical transmit or receive signal (− differential).
PAGE 16
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081RNB (Continued) Pin Number Pin Name 17 VDDIO Type (6) P Pin Function 3.3V, 2.5V, or 1.8V digital VDD. RMII Mode: RMII Carrier Sense/Receive Data Valid Output. 18 CRS_DV/ CONFIG2 Ipd/O Config Mode: The pull-up/pull-down value is latched as CONFIG2 at the de-assertion of reset. See the Strapping Options – KSZ8081RNB section for details. RMII Mode: 25MHz Mode. This pin provides the 50MHz RMII reference clock output to the MAC.
PAGE 17
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Pin Description – KSZ8081RNB (Continued) Pin Number Pin Name Type (6) Pin Function LED Output: Programmable LED0 Output. Config Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) at the deassertion of reset. See the Strapping Options – KSZ8081RNB section for details.
PAGE 18
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Strapping Options – KSZ8081RNB The strap-in pins are latched at the de-assertion of reset. In some systems, the MAC RMII receive input pins may drive high/low during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched to unintended high/low states. In this case, external pull-ups (4.7kΩ) or pull-downs (1.0kΩ) should be added on these PHY strap-in pins to ensure that the intended values are strapped-in correctly.
PAGE 19
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Functional Description: 10Base-T/100Base-TX Transceiver The KSZ8081 is an integrated single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3 Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2V core.
PAGE 20
Micrel, Inc. KSZ8081MNX/KSZ8081RNB 10Base-T Receive On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400mV, or with short pulse widths, to prevent noise at the RXP and RXM inputs from falsely triggering the decoder.
PAGE 21
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Figure 1. Auto-Negotiation Flow Chart August 19, 2015 21 Revision 1.
PAGE 22
Micrel, Inc. KSZ8081MNX/KSZ8081RNB MII Interface (KSZ8081MNX Only) The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface between MII PHYs and MACs, and has the following key characteristics: • Pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). • 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
PAGE 23
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Transmit Data[3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC. When TXEN is asserted, TXD[3:0] are accepted by the PHY for transmission. TXD[3:0] is 00 to indicate idle when TXEN is de-asserted. Values other than 00 on TXD[3:0] while TXEN is de-asserted are ignored by the PHY. Receive Clock (RXC) RXC provides the timing reference for RXDV, RXD[3:0], and RXER. • In 10Mbps mode, RXC is recovered from the line while the carrier is active.
PAGE 24
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Figure 2. KSZ8081MNX MII Interface August 19, 2015 24 Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB RMII Data Interface (KSZ8081RNB Only) The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It provides a common interface between physical layer and MAC layer devices, and has the following key characteristics: • • • • Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50MHz reference clock). 10Mbps and 100Mbps data rates are supported at both half- and full-duplex.
PAGE 26
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Transmit Enable (TXEN) TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated before the first REF_CLK following the final dibit of a frame. TXEN transitions synchronously with respect to REF_CLK. Transmit Data[1:0] (TXD[1:0]) TXD[1:0] transitions synchronously with respect to REF_CLK.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Figure 3. KSZ8081RNB RMII Interface (25MHz Clock Mode) Figure 4. KSZ8081RNB RMII Interface (50MHz Clock Mode) August 19, 2015 27 Revision 1.
PAGE 28
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Back-to-Back Mode – 100Mbps Copper Repeater Two KSZ8081MNX/RNB devices can be connected back-to-back to form a 100Base-TX copper repeater. Figure 5. KSZ8081MNX/RNB to KSZ8081MNX/RNB Back-to-Back Copper Repeater MII Back-to-Back Mode (KSZ8081MNX Only) In MII back-to-back mode, a KSZ8081MNX interfaces with another KSZ8081MNX to provide a complete 100Mbps copper repeater solution.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB RMII Back-to-Back Mode (KSZ8081RNB Only) In RMII back-to-back mode, a KSZ8081RNB interfaces with another KSZ8081RNB to provide a complete 100Mbps copper repeater solution. The KSZ8081RNB devices are configured to RMII back-to-back mode after power-up or reset with the following: • Strapping pin CONFIG[2:0] (Pins 18, 29, 28) set to 101 • A common 50MHz reference clock connected to XI (Pin 9) of both KSZ8081RNB devices • RMII signals connected as shown in Table 4.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Table 5.
PAGE 31
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Straight Cable A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 6 shows a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device). Figure 6. Typical Straight Cable Connection Crossover Cable A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
PAGE 32
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Loopback Mode The KSZ8081MNX/RNB supports the following loopback operations to verify analog and/or digital data paths. • Local (digital) loopback • Remote (analog) loopback Local (Digital) Loopback This loopback mode checks the MII/RMII transmit and receive data paths between the KSZ8081MNX/RNB and the external MAC, and is supported for both speeds (10/100Mbps) at full-duplex. The loopback data path is shown in Figure 8. 1.
PAGE 33
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Remote (Analog) Loopback This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and receive data paths between the KSZ8081MNX/RNB and its link partner, and is supported for 100Base-TX full-duplex mode only. The loopback data path is shown in Figure 9. 1. The Fast Ethernet (100Base-TX) PHY link partner transmits frames to the KSZ8081MNX/RNB. 2. Frames are wrapped around inside the KSZ8081MNX/RNB. 3.
PAGE 34
Micrel, Inc. KSZ8081MNX/KSZ8081RNB LinkMD® Cable Diagnostic The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems. These include open circuits, short circuits, and impedance mismatches. LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the shape of the reflected signal to determine the type of fault.
PAGE 35
Micrel, Inc. KSZ8081MNX/KSZ8081RNB NAND Tree Support The KSZ8081MNX/RNB provides parametric NAND tree support for fault detection between chip I/Os and board. The NAND tree is a chain of nested NAND gates in which each KSZ8081MNX/RNB digital I/O (NAND tree input) pin is an input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND gates.
PAGE 36
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Table 8. NAND Tree Test Pin Order for KSZ8081RNB Pin Number Pin Name NAND Tree Description 11 MDIO Input 12 MDC Input 15 RXD1 Input 16 RXD0 Input 18 CRS_DV Input 19 REF_CLK Input 21 INTRP Input 23 TXEN Input 31 LED1 Input 30 LED0 Input 24 TXD0 Input 25 TXD1 Output NAND Tree I/O Testing Use the following procedure to check for faults on the KSZ8081MNX/RNB digital I/O pin connections to the board: 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Power Management The KSZ8081MNX/RNB incorporates a number of power-management modes and features that provide methods to consume less energy. These are discussed in the following sections. Power-Saving Mode Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link).
PAGE 38
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Reference Circuit for Power and Ground Connections The KSZ8081MNX/RNB is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and ground connections are shown in Figure 10 and Table 9 for 3.3V VDDIO. Figure 10. KSZ8081MNX/RNB Power and Ground Connections Table 9. KSZ8081MNX/RNB Power Pin Descriptions Power Pin Pin Number VDD_1.2 2 VDDA_3.3 3 VDDIO 17 August 19, 2015 Description Decouple with 2.2µF and 0.
PAGE 39
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Typical Current/Power Consumption Table 10, Table 11, and Table 12 show typical values for current consumption by the transceiver (VDDA_3.3) and digital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081MNX/RNB device for the indicated nominal operating voltages. These current and power consumption values include the transmit driver current and on-chip regulator current for the 1.2V core. Transceiver (3.3V), Digital I/Os (3.3V) Table 10.
PAGE 40
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Transceiver (3.3V), Digital I/Os (1.8V) Table 12. Typical Current/Power Consumption (VDDA_3.3 = 3.3V, VDDIO = 1.8V) 3.3V Transceiver (VDDA_3.3) 1.8V Digital I/Os (VDDIO) Total Chip Power mA mA mW 100Base-TX Link-up (no traffic) 34 11 132 100Base-TX Full-duplex @ 100% utilization 34 12 134 10Base-T Link-up (no traffic) 15 9.0 65.7 10Base-T Full-duplex @ 100% utilization 27 9.0 105 Power-saving mode (Reg. 1Fh, Bit [10] = 1) 15 9.0 65.
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Micrel, Inc.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description Address Name (10) Description Mode Default Register 0h – Basic Control 1 = Software reset 0.15 Reset 0 = Normal operation RW/SC 0 RW 0 This bit is self-cleared after a ‘1’ is written to it. 0.14 Loopback 1 = Loopback mode 0 = Normal operation 1 = 100Mbps 0.13 Speed Select Set by the SPEED strapping pin. 0 = 10Mbps RW This bit is ignored if auto-negotiation is enabled (Register 0.12 = 1).
PAGE 43
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 1h – Basic Status 1 = T4 capable 1.15 100Base-T4 1.14 100Base-TX Full-Duplex 1 = Capable of 100Mbps full-duplex 1.13 100Base-TX Half-Duplex 1 = Capable of 100Mbps half-duplex 1.12 10Base-T Full-Duplex 1 = Capable of 10Mbps full-duplex 1.11 10Base-T Half-Duplex 1 = Capable of 10Mbps half-duplex 1.10:7 Reserved 1.6 No Preamble 1.5 AutoNegotiation Complete 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 4h – Auto-Negotiation Advertisement 4.15 Next Page 4.14 Reserved 4.13 Remote Fault 4.12 Reserved 1 = Next page capable 0 = No next page capability Reserved 1 = Remote fault supported 0 = No remote fault Reserved RW 0 RO 0 RW 0 RO 0 RW 00 RO 0 [00] = No pause 4.
PAGE 45
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 5h – Auto-Negotiation Link Partner Ability 5.7 100Base-TX Half-Duplex 1 = 100Mbps half-duplex capable 5.6 10Base-T Full-Duplex 1 = 10Mbps full-duplex capable 5.5 10Base-T Half-Duplex 1 = 10Mbps half-duplex capable 5.4:0 Selector Field 0 = No 100Mbps half-duplex capability 0 = No 10Mbps full-duplex capability 0 = No 10Mbps half-duplex capability [00001] = IEEE 802.
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Micrel, Inc.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 16h – Operation Mode Strap Override 16.8 Reserved 16.7 MII B-to-B Override RMII B-to-B Override 16.6 16.5 NAND Tree Override 16.4:2 Reserved 16.1 RMII Override 16.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 18h – Expanded Control 18.15:12 Reserved Reserved RW 0000 RW 1 RW 0 RW 00_0 RW 0 RW 00_0000 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 Energy-detect power-down mode EDPD Disabled 18.11 1 = Disable 0 = Enable See also Register 10h, Bit [4] for PLL off. 1 = MII output is random latency 100Base-TX Latency 18.
PAGE 49
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 1Bh – Interrupt Control/Status 1 = Jabber occurred 1B.7 Jabber Interrupt 1B.6 Receive Error Interrupt 1 = Receive error occurred 1B.5 Page Receive Interrupt 1 = Page receive occurred 1B.4 Parallel Detect Fault Interrupt 1 = Parallel detect fault occurred 1B.3 Link Partner Acknowledge Interrupt 1 = Link partner acknowledge occurred 1B.2 Link-Down Interrupt 1B.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default RO 0000_00 RO 0 RO 0 Register 1Eh – PHY Control 1 1E.15:10 Reserved 1E.9 Enable Pause (Flow Control) 1E.8 Link Status 1E.7 Polarity Status 1E.6 Reserved Reserved 1E.5 MDI/MDI-X State 1 = MDI-X 1E.4 Energy Detect 1E.
PAGE 51
Micrel, Inc. KSZ8081MNX/KSZ8081RNB Register Description (Continued) Address Name (10) Description Mode Default Register 1Fh – PHY Control 2 1 = Force link pass 0 = Normal link operation 1F.11 Force Link 1F.10 Power Saving 1F.9 Interrupt Level 1F.8 Enable Jabber 1F.7 RMII Reference Clock Select This bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Absolute Maximum Ratings(11) Operating Ratings(12) Supply Voltage (VIN) (VDD_1.2) .................................................. –0.5V to +1.8V (VDDIO, VDDA_3.3) ...................................... –0.5V to +5.0V Input Voltage (all inputs) .............................. –0.5V to +5.0V Output Voltage (all outputs) ......................... –0.5V to +5.0V Lead Temperature (soldering, 10s) ............................ 260°C Storage Temperature (TS) ................
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Electrical Characteristics(13) (Continued) Symbol Parameter Condition Min. Typ. Max. VDDIO = 3.3V 30 45 73 VDDIO = 2.5V 39 61 102 VDDIO = 1.8V 48 99 178 VDDIO = 3.3V 26 43 79 VDDIO = 2.5V 34 59 113 VDDIO = 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Timing Diagrams MII SQE Timing (10Base-T) Figure 11. MII SQE Timing (10Base-T) Table 13. MII SQE Timing (10Base-T) Parameters Timing Parameter Description tP TXC period 400 ns tWL TXC pulse width low 200 ns tWH TXC pulse width high 200 ns tSQE COL (SQE) delay after TXEN de-asserted 2.2 µs tSQEP COL (SQE) pulse duration 1.0 µs August 19, 2015 Min. 54 Typ. Max. Units Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MII Transmit Timing (10Base-T) Figure 12. MII Transmit Timing (10Base-T) Table 14.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MII Receive Timing (10Base-T) Figure 13. MII Receive Timing (10Base-T) Table 15. MII Receive Timing (10Base-T) Parameters Timing Parameter Description tP RXC period 400 ns tWL RXC pulse width low 200 ns tWH RXC pulse width high 200 ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC 205 ns tRLAT CRS to (RXDV, RXD[3:0]) latency 7.2 µs August 19, 2015 Min. 56 Typ. Max. Units Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MII Transmit Timing (100Base-TX) Figure 14. MII Transmit Timing (100Base-TX) Table 16.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MII Receive Timing (100Base-TX) Figure 15. MII Receive Timing (100Base-TX) Table 17. MII Receive Timing (100Base-TX) Parameters Timing Parameter Description tP RXC period 40 ns tWL RXC pulse width low 20 ns tWH RXC pulse width high 20 ns tOD (RXDV, RXD[3:0], RXER) output delay from rising edge of RXC tRLAT CRS to (RXDV, RXD[3:0] latency August 19, 2015 Min. 16 Typ. 21 170 58 Max. 25 Units ns ns Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB RMII Timing Figure 16. RMII Timing – Data Received from RMII Figure 17. RMII Timing – Data Input to RMII Table 18. RMII Timing Parameters – KSZ8081RNB (25MHz input to XI pin, 50MHz output from REF_CLK pin) Timing Parameter Description Min. Typ. Max. tCYC Clock cycle t1 Setup time 4 ns t2 Hold time 2 ns tOD Output delay 7 10 13 ns Min. Typ. Max. Units 20 Units ns Table 19.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Auto-Negotiation Timing Figure 18. Auto-Negotiation Fast Link Pulse (FLP) Timing Table 20. Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters Timing Parameter Description tBTB FLP burst to FLP burst tFLPW FLP burst width tPW Clock/Data pulse width tCTD Clock pulse to data pulse 55.5 64 69.5 µs tCTC Clock pulse to clock pulse 111 128 139 µs Number of clock/data pulses per FLP burst 17 August 19, 2015 60 Min. Typ. Max.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MDC/MDIO Timing Figure 19. MDC/MDIO Timing Table 21. MDC/MDIO Timing Parameters Timing Parameter Description fc Typ. Max. Units MDC Clock Frequency 2.5 10 MHz tP MDC period 400 tMD1 MDIO (PHY input) setup to rising edge of MDC 10 ns tMD2 MDIO (PHY input) hold from rising edge of MDC 4 ns tMD3 MDIO (PHY output) delay from rising edge of MDC 5 August 19, 2015 Min. 61 222 ns ns Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Power-up/Reset Timing The KSZ8081MNX/RNB reset timing requirement is summarized in Figure 20 and Table 22. Figure 20. Power-up/Reset Timing Table 22. Power-up/Reset Timing Parameters Parameter Description Min. Max. Units tVR Supply voltage (VDDIO, VDDA_3.3) rise time 300 µs tSR Stable supply voltage (VDDIO, VDDA_3.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Reset Circuit Figure 21 shows a reset circuit recommended for powering up the KSZ8081MNX/RNB if reset is triggered by the power supply. Figure 21. Recommended Reset Circuit Figure 22 Shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Reference Circuits – LED Strap-In Pins The pull-up, float, and pull-down reference circuits for the LED1/SPEED and LED0/NWAYEN strapping pins are shown in Figure 23 for 3.3V and 2.5V VDDIO. Figure 23. Reference Circuits for LED Strapping Pins For using 1.8V VDDIO, should select parts with low 1.8V operation voltage and forwarding current IF about 2mA LED indicator.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Reference Clock – Connection and Selection A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081MNX/RNB. For the KSZ8081MNX in all operating modes and for the KSZ8081RNB in RMII – 25MHz Clock Mode, the reference clock is 25MHz. The reference clock connections to XI (Pin 9) and XO (Pin 8), and the reference clock selection criteria, are provided in Figure 24 and Table 23. Figure 24.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Magnetic – Connection and Selection A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs exceeding FCC requirements. The KSZ8081MNX/RNB design incorporates voltage-mode transmit drivers and on-chip terminations. With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential pairs.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Table 25 lists recommended magnetic characteristics. Table 25. Magnetics Selection Criteria Parameter Value Test Condition Turns ratio 1 CT : 1 CT Open-circuit inductance (minimum) 350µH 100mV, 100kHz, 8mA Insertion loss (typical) –1.1dB 100kHz to 100MHz HIPOT (minimum) 1500Vrms Table 26 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side that can be used with the KSZ8081MNX/RNB. Table 26.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB Package Information and Recommended Land Pattern(16) 32-Pin 5mm × 5mm QFN Note: 16. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. August 19, 2015 68 Revision 1.
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Micrel, Inc. KSZ8081MNX/KSZ8081RNB MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel, Inc. is a leading global manufacturer of IC solutions for the worldwide high performance linear and power, LAN, and timing & communications markets.