Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 8  2017 Microchip Technology Inc.
TABLE 2-1: SIGNALS FOR KSZ8041TL/FTL
Pin
Number
Pin Name
Type
(Note
2-1)
Description
1 GND GND Ground
2 GND GND Ground
3 GND GND Ground
4 VDDA_1.8 P 1.8V analog V
DD
5 VDDA_1.8 P
1.8V analog V
DD
6 V1.8_OUT P
1.8V output voltage from chip
7 VDDA_3.3 P
3.3V analog V
DD
8 VDDA_3.3 P 3.3V analog V
DD
9 RX– I/O Physical receive or transmit signal (– differential)
10 RX+ I/O Physical receive or transmit signal (+ differential)
11 TX– I/O Physical transmit or receive signal (– differential)
12 TX+ I/O Physical transmit or receive signal (+ differential)
13
GND GND Ground
14 XO O
Crystal feedback
This pin is used only in MII mode when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used, or if RMII
mode or SMII mode is selected.
15
XI/REFCLK/
CLOCK
I
Crystal/Oscillator/External Clock Input
MII Mode: 25 MHz ±50 ppm (crystal, oscillator, or external clock)
RMII Mode: 50 MHz ±50 ppm (oscillator, or external clock only)
SMII Mode: 125 MHz ±100 ppm (oscillator, or external clock only)
16 REXT I/O
Set physical transmit output current
Connect a 6.49 k resistor in parallel with a 100 pF capacitor to ground on
this pin. See KSZ8041TL-FTL reference schematics.
17
GND GND Ground
18 MDIO I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7 k pull-up resistor.
19 MDC I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3/
PHYAD0
Ipu/O
MII Mode: Receive Data Output[3](Note 2-2)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during
power-up/reset. See Table 2-2 for details.
21
RXD2/
PHYAD1
Ipd/O
MII Mode: Receive Data Output[2](Note 2-2)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during
power-up/reset. See Table 2-2 for details.