Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 54  2017 Microchip Technology Inc.
7.11 Reset Circuit
The following reset circuit is recommended for powering up the KSZ8041TL/FTL/MLL if reset is triggered by the power
supply.
The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or
FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL/MLL device.
The RST_OUT_n from CPU/FPGA provides the warm reset after power up.
The following figure shows the reference circuits for pull-up, float and pull-down on the LED1 and LED0 strap-in pins.
FIGURE 7-13: RECOMMENDED RESET CIRCUIT
FIGURE 7-14: RECOMMENDED RESET CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET
OUTPUT
KSZ8041TL/FTL/MLL
3.3V
D1
D1: 1N4148
R 10Nȍ
C 10μF
RST#
KSZ8041TL/FTL/MLL CPU/FPGA
3.3V
C 10μF
R 10Nȍ
RST_OUT_n
D1
D2
D1, D2: 1N4148
RST#