Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 18  2017 Microchip Technology Inc.
Ipu/O = Input with internal pull-up (40 k ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40 k ±30%) during power-up/reset; output pin otherwise.
Ipu = Input with internal pull-up. (40 k ±30%)
Ipd = Input with internal pull-down. (40 k ±30%)
Opu = Output with internal pull-up. (40 k ±30%)
Note 2-2 MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0]
presents valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted.
Note 2-3 MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0]
presents valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-
asserted.
Note 2-1 Ipu/O = Input with internal pull-up (40 k ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40 k ±30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII signals to be latched high. In this case, it
is recommended to add 1 k pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to ISOLATE
mode, or is not configured with an incorrect PHY Address.
TABLE 2-4: STRAP-IN OPTIONS KSZ8041MLL
Pin
Number
Pin Name
Type
Note 2-1
Description
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY Address is latched at power-up / reset and is configurable to any
value from 1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up / reset and are defined
as follows:
CONFIG[2:0] Mode
000 MII (default)
001 Reserved - not used
010 Reserved - not used
011 Reserved - not used
100 MII 100 Mbps Preamble Restore
101 Reserved - not used
110 MII Back-to-Back
111 Reserved - not used
29 ISO Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up/reset, this pin value is latched into register 0h bit 10.
43 SPEED Ipu/O
SPEED mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
During power-up/reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Advertise-
ment) as the Speed capability support.
23 DUPLEX Ipu/O
DUPLEX mode
Pull-up (default) = Half-Duplex
Pull-down = Full-Duplex
During power-up/reset, this pin value is latched into register 0h bit 8 as the
Duplex Mode.
42 NWAYEN Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up/reset, this pin value is latched into register 0h bit 12.