Datasheet

KSZ8041NL/RNL
DS00002245B-page 8  2017 Microchip Technology Inc.
21 INTRP Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for program-
ming the interrupt conditions and reading the interrupt status. Regis-
ter 1Fh bit 9 sets the interrupt output to active low (default) or active
high.
22 TXC O
MII mode: Transmit Clock Output
23
TXEN /
TX_EN
I
MII mode: Transmit Enable Input
RMII mode: Transmit Enable Input
24
TXD0 /
TXD[0]
I
MII mode: Transmit Data Input[0]
(Note 2-4)
RMII mode: Transmit Data Input[0]
(Note 2-5)
25
TXD1 /
TXD[1]
I
MII mode: Transmit Data Input[1] (Note 2-4)
RMII mode: Transmit Data Input[1] (Note 2-5)
26 TXD2 I
MII mode: Transmit Data Input[2] (Note 2-4)
27 TXD3 I MII mode: Transmit Data Input[3]
(Note 2-4)
28 COL/CONFIG0 Ipd/O
MII mode: Collision Detect Output
Config mode: The pull-up/pull-down value is latched as CONFIG0
during power-up or reset. See “Strap-In option – KSZ8041NL” for
details.
29 CRS/CONFIG1 Ipd/O
MII mode: Collision Sense Output
Config mode: The pull-up/pull-down value is latched as CONFIG1
during power-up or reset. See “Strap-In option – KSZ8041NL” for
details.
TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED)
Pin Number Symbol
Buffer Type
(Note 2-1)
Description