Datasheet

 2017 Microchip Technology Inc. DS00002245B-page 47
KSZ8041NL/RNL
7.9 Power-Up/Reset Timing
The KSZ8041NL/RNL reset timing requirement is summarized in Figure 7-10 and Figure 7-10.
FIGURE 7-10: POWER-UP/RESET TIMING
The supply voltage (V
DDIO
_3.3 and V
DDA
_3.3) power-up waveform should be monotonic. The 250 µs minimum rise time
is from 10% to 90%.
After the deassertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM
(MDC/MDIO) Interface.
TABLE 7-10: POWER-UP/RESET TIMING PARAMETERS
Parameters Description Min Max Units
t
VR
Supply Voltage (V
DDIO
_3.3, V
DDA
_3.3) Rise
Time
250 — µs
t
sr
Stable Supply Voltage to Reset High 10 — ms
t
cs
Configuration Setup Time 5 — ns
t
ch
Configuration Hold Time 5 — ns
t
rc
Reset to Strap-In Pin Output 6 — ns