Datasheet

KSZ8041NL/RNL
DS00002245B-page 30  2017 Microchip Technology Inc.
4.2 Register Descriptions
Table 4-2 provides a list of supported registers and their descriptions.
TABLE 4-2: REGISTER DESCRIPTIONS
Address Name Description
Mode
(Note 4-1)
Default
Register 0h – Basic Control
0.15 Reset
1 = Software reset
0 = Normal operation
This bit is self-cleared after a ‘1’
is written to it.
RW/SC 0
0.14 Loop-Back
1 = Loop-back mode
0 = Normal operation
RW 0
0.13 Speed Select (LSB)
1 = 100 Mbps
0 = 10 Mbps
This bit is ignored if auto-negotia-
tion is enabled (register 0.12 =
1).
RW
Set by SPEED strapping
pin.
See Ta b le 2-2 and
Table 2-4 for details.
0.12 Auto-Negotiation Enable
1 = Enable auto-negotiation
process
0 = Disable auto-negotiation
process
If enabled, auto-negotiation
result overrides the settings in
register 0.13 and 0.8.
RW
Set by NWAYEN strap-
ping pin.
See Ta b le 2-2 and
Table 2-4 for details.
0.11 Power Down
1 = Power-down mode
0 = Normal operation
RW 0
0.10 Isolate
1 = Electrical isolation of PHY
from MII and TX+/TX-
0 = Normal operation
RW
Set by ISO strapping pin.
See Ta b le 2-2 and
Table 2-4 for details.
0.9 Restart Auto-Negotiation
1 = Restart auto-negotiation
process
0 = Normal operation
This bit is self-cleared after a ‘1’
is written to it.
RW/SC 0
0.8 Duplex Mode
1 = Full-duplex
0 = Half-duplex
RW
Inverse of DUPLEX
strapping pin value.
See Ta b le 2-2 and
Table 2-4 for details.
0.7 Collision Test
1 = Enable COL test
0 = Disable COL test
RW 0
0.6:1 Reserved RO 000_000
0.0
Disable
Transmitter
0 = Enable transmitter
1 = Disable transmitter
RW 0
Register 1h – Basic Status
1.15 100BASE-T4
1 = T4 capable
0 = Not T4 capable
RO 0
1.14 100BASE-TX Full Duplex
1 = Capable of 100 Mbps full-
duplex
0 = Not capable of 100 Mbps full-
duplex
RO 1