Datasheet

KSZ8041NL/RNL
DS00002245B-page 20  2017 Microchip Technology Inc.
Table 3-1 shows the MII Management frame format for the KSZ8041NL/RNL.
3.10 Interrupt (INTRP)
INTRP (pin 21) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041NL/RNL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits and are used to
enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits,
and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading
register 1Bh.
Bit 9 of register 1Fh sets the interrupt level to active high or active low.
3.11 MII Data Interface (KSZ8041NL only)
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
• Supports 10 Mbps and 100 Mbps data rates
• Uses a 25-MHz reference clock, sourced by the PHY
• Provides independent 4-bit wide (nibble) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception
By default, the KSZ8041NL is configured to MII mode after it is powered up or reset with the following:
• A 25-MHz crystal connected to XI, XO (pins 9, 8), or an external 25-MHz clock source (oscillator) connected to XI
• CONFIG[2:0] (pins 18, 29, 28) set to ‘000’ (default setting)
3.12 MII Signal Definition (KSZ8041NL only)
Table 3-2 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 specification for detailed information.
TABLE 3-1: MII MANAGEMENT FRAME FORMAT
Preamble
Start of
Frame
Read/
Write
OP
Code
PHY
Address
Bits
[4:0]
REG
Address
Bits
[4:0]
TA
Data Bits [15:0]
Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
TABLE 3-2: MII SIGNAL DEFINITION
MII Signal
Name
Direction (with
respect to PHY,
KSZ8041NL signal)
Direction
(with respect to MAC)
Description
TXC Output Input
Transmit Clock
(2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data [3:0]
RXC Output Input
Receive Clock
(2.5 MHz for 10 Mbps, 25 MHz for 100 Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data [3:0]
RXER Output Input, or (not required) Receive Error
CRS Output Input Carrier Sense
COL Output Input Collision Detection