KSZ8041NL/RNL 10BASE-T/100BASE-TX Physical Layer Transceiver Highlights • Single-Chip Ethernet Physical Layer Transceiver (PHY) • HP Auto-MDIX Support Target Applications • • • • • • Printer LOM Game Console IPTV IP Phone IP Set-Top Box DS00002245B-page 1 Key Benefits • Single-Chip 10BASE-T/100BASE-TX Physical Layer Solution • Fully Compliant To IEEE 802.
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KSZ8041NL/RNL Table of Contents 1.0 General Description ........................................................................................................................................................................ 4 2.0 Pin Description and Configuration .................................................................................................................................................. 6 3.0 Functional Description .......................................................................
KSZ8041NL/RNL 1.0 GENERAL DESCRIPTION The KSZ8041NL is a single supply 10BASE-T/100BASE-TX physical layer transceiver, which provides MII/RMII interfaces to transmit and receive data. A unique mixed-signal design extends signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables.
KSZ8041NL/RNL FIGURE 1-2: KSZ8041RNL FUNCTIONAL DIAGRAM TX+ TX- Transmitter 10/100 Pulse Shaper NRZ/NRZI MLT3 Encoder 4B/5B Encoder Scrambler Parallel/Serial MDC MDIO TX_EN TXD1 TXD0 Parallel/Serial Manchester Encoder REXT RMII Adaptive EQ Base Line Wander Correction MLT3 Decoder NRZI/NRZ RX+ RX- Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel CRS_DV RXD1 RXD0 RX_ER REF_CLK Auto Negotiation 10Base-T Receiver Manchester Decoder Serial/Parallel INTRP Power Down RST# Power Saving
KSZ8041NL/RNL 2.0 PIN DESCRIPTION AND CONFIGURATION 2.1 KSZ8041NL Pin Description and Configuration TXD1/TXD[1] KSZ8041NL 32-QFN PIN ASSIGNMENT (TOP VIEW) RST# LED1/SPEED LED0/NWAYEN CRS/CONFIG1 COL/CONFIG0 TXD3 TXD2 FIGURE 2-1: 32 31 30 29 28 27 26 25 GND VDDPLL_1.8 VDDA_3.3 RXRX+ TX- 1 24 2 23 3 22 6 19 TXD0/TXD[0] TXEN/TX_EN TXC INTRP RXER/RX_ER/ISO RXC TX+ 7 18 RXDV/CRSDV/CONFIG2 XO 8 17 VDDIO_3.
KSZ8041NL/RNL TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) 7 TX+ I/O Physical transmit or receive signal (+ differential) Description 8 XO O Crystal Feedback. This pin is used only in MII mode when a 25-MHz crystal is used. This pin is a no connect if an oscillator or an external clock source is used, or if RMII mode is selected.
KSZ8041NL/RNL TABLE 2-1: KSZ8041NL PIN DESCRIPTION (CONTINUED) Pin Number Symbol Buffer Type (Note 2-1) Description Interrupt Output: Programmable Interrupt Output Register 1Bh is the Interrupt Control/Status Register for programming the interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the interrupt output to active low (default) or active high.
KSZ8041NL/RNL TABLE 2-1: Pin Number KSZ8041NL PIN DESCRIPTION (CONTINUED) Symbol Buffer Type (Note 2-1) Description LED Output: Programmable LED0 Output Config ode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up or reset. See Strap-In option – KSZ8041NL for details.
KSZ8041NL/RNL TABLE 2-1: Pin Number KSZ8041NL PIN DESCRIPTION (CONTINUED) Symbol Buffer Type (Note 2-1) Description LED Output: Programmable LED1 Output Config mode: Latched as SPEED (register 0h, bit 13) during powerup or reset. See Strap-In option – KSZ8041NL for details.
KSZ8041NL/RNL 2.2 STRAP-IN OPTION – KSZ8041NL Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISOLATE mode, or is not configured with an incorrect PHY Address.
KSZ8041NL/RNL KSZ8041RNL Pin Description and Configuration LED1 / SPEED LED0 / NWAYEN CONFIG1 CONFIG0 NC NC TXD1 KSZ8041RNL 32-QFN PIN ASSIGNMENT (TOP VIEW) RST# FIGURE 2-2: 32 31 30 29 28 27 26 25 TX_EN VDDA_3.3 3 22 NC RX- 4 Paddle Ground 21 INTRP RX+ 5 (on bottom of chip) 20 RX_ER / ISO TX- 6 19 REF_CLK TX+ 7 18 CRS_DV / CONFIG2 XO 8 17 VDDIO_3.3 TABLE 2-3: 9 10 11 12 13 14 15 16 RXD0 / DUPLEX 23 RXD1 / PHYAD2 2 PHYAD1 VDDPLL_1.
KSZ8041NL/RNL TABLE 2-3: KSZ8041RNL PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type (Note 2-1) Pin Function 11 MDIO I/O Management Interface (MII) Data I/O This pin requires an external 4.7-k pull-up resistor. 12 MDC I Management Interface (MII) Clock Input This pin is synchronous to the MDIO data interface. 13 PHYAD0 Ipu/O The pull-up/pull-down value is latched as PHYADDR[0] during power-up or reset. See Strap-In option – KSZ8041RNL for details.
KSZ8041NL/RNL TABLE 2-3: KSZ8041RNL PIN DESCRIPTION (CONTINUED) Pin Number Pin Name Type (Note 2-1) Pin Function LED Output: Programmable LED0 Output Config mode: Latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up or reset. See Strap-In option – KSZ8041RNL for details.
KSZ8041NL/RNL Note 2-1 P = Power supply Gnd = Ground I = Input O = Output I/O = Bi-directional Opu = Output with internal pull-up (40K ±30%) Ipu/O = Input with internal pull-up (40K ±30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40K ±30%) during power-up/reset; output pin otherwise. Note 2-2 RMII Rx mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which CRS_DV is asserted, two bits of recovered data are sent from the PHY.
KSZ8041NL/RNL 2.4 STRAP-IN OPTION – KSZ8041RNL Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during power-up or reset, and consequently cause the PHY strap-in pins on the RMII signals to be latched high. In this case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap in to ISOLATE mode, or is not configured with an incorrect PHY Address.
KSZ8041NL/RNL 3.0 FUNCTIONAL DESCRIPTION The KSZ8041NL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u specification. On the media side, the KSZ8041NL supports 10BASE-T and 100BASE-TX with HP auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. The KSZ8041NL offers a choice of MII or RMII data interface connection with the MAC processor.
KSZ8041NL/RNL 3.6 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and RX- inputs from falsely triggering the decoder.
KSZ8041NL/RNL FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART Start Auto Negotiation N o Force Link Setting Parallel Operation Yes Bypass Auto Negotiation and Set Link Mode Attempt Auto Negotiation Listen for 100BASE-TX Idles Listen for 10BASE-T Link Pulses No Join Flow Link Mode Set ? Yes Link Mode Set 3.9 MII Management (MIIM) Interface The KSZ8041NL/RNL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input or Output (MDIO) Interface.
KSZ8041NL/RNL Table 3-1 shows the MII Management frame format for the KSZ8041NL/RNL. TABLE 3-1: MII MANAGEMENT FRAME FORMAT Preamble Start of Frame Read/ Write OP Code Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z 3.
KSZ8041NL/RNL 3.12.1 TRANSMIT CLOCK (TXC) TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for Transmit Enable (TXEN) and Transmit Data [3:0] (TXD[3:0]). TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation. 3.12.2 TRANSMIT ENABLE (TXEN) TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission.
KSZ8041NL/RNL 3.13 Reduced MII (RMII) Data Interface The Reduced Media Independent Interface (RMII) specifies a low pin count MII.
KSZ8041NL/RNL The KSZ8041NL inputs the 50-MHz REF_CLK from the MAC or system board. The KSZ8041RNL generates the 50MHz RMII REF_CLK and outputs it to the MAC. 3.14.2 TRANSMIT ENABLE (TX_EN) TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is negated prior to the first REF_CLK following the final di-bit of a frame.
KSZ8041NL/RNL 3.15 RMII Signal Diagram The KSZ8041NL RMII pin connections to the MAC are shown in Figure 3-2.
KSZ8041NL/RNL 3.16 HP Auto MDI/MDI-X HP Auto MDI/MDI-X configuration eliminates the confusion of whether to use a straight cable or a crossover cable between the KSZ8041NL/RNL and its link partner. This feature allows the KSZ8041NL/RNL to use either type of cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and receive pairs from the link partner, and then assigns transmit and receive pairs of the KSZ8041NL/RNL accordingly.
KSZ8041NL/RNL 3.16.1 STRAIGHT CABLE A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-4 depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X). FIGURE 3-4: 3.16.2 TYPICAL STRAIGHT CABLE CONNECTION CROSSOVER CABLE A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
KSZ8041NL/RNL 3.17 Power Management The KSZ8041NL/RNL offers the following two power management modes: • Power Saving Mode This mode is used to reduce power consumption when the cable is unplugged. It is in effect when the auto-negotiation mode is enabled, the cable is disconnected, and register 1F bit 10 is set to 1. Under the power saving mode, the KSZ8041NL/RNL shuts down all transceiver blocks, except for transmitter, energy detect, and PLL circuits.
KSZ8041NL/RNL FIGURE 3-8: KSZ8041NL/RNL POWER AND GROUND CONNECTIONS Ferrite Bead ` ` 22uF VOUT VIN 3 VDDA_3.3 1.8V Low Noise Regulator (integrated) 0.1uF 1.0uF 0.1uF VDDPLL_1.8 2 17 3.3V VDDIO_3.3 ` 22uF 0.1uF KSZ8041NL/RNL GND 1 TABLE 3-6: Power Pin Paddle KSZ8041NL/RNL POWER PIN DESCRIPTION Pin Number Description VDDPLL_1.8 2 Decouple with 1.0 µF and 0.1 µF capacitors to ground. VDDA_3.3 3 Connect to the board’s 3.3V supply through ferrite bead. VDDIO_3.
KSZ8041NL/RNL 4.0 REGISTERS 4.1 Register Map Table 4-1 summarizes the register map.
KSZ8041NL/RNL 4.2 Register Descriptions Table 4-2 provides a list of supported registers and their descriptions. TABLE 4-2: REGISTER DESCRIPTIONS Address Name Description Mode (Note 4-1) Default RW/SC 0 RW 0 RW Set by SPEED strapping pin. See Table 2-2 and Table 2-4 for details. Register 0h – Basic Control 0.15 Reset 1 = Software reset 0 = Normal operation This bit is self-cleared after a ‘1’ is written to it. 0.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Mode (Note 4-1) Default 100BASE-TX Half Duplex 1 = Capable of 100 Mbps halfduplex 0 = Not capable of 100 Mbps half-duplex RO 1 10BASE-T Full Duplex 1 = Capable of 10 Mbps fullduplex 0 = Not capable of 10 Mbps fullduplex RO 1 10BASE-T Half Duplex 1 = Capable of 10 Mbps halfduplex 0 = Not capable of 10 Mbps halfduplex RO 1 Reserved — RO 0000 No Preamble 1 = Preamble suppression 0 = Normal preamble RO 1 1.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default Register 4h – Auto-Negotiation Advertisement 4.15 Next Page 1 = Next page capable 0 = No next page capability RW 0 4.14 Reserved — RO 0 4.13 Remote Fault 1 = Remote fault supported 0 = No remote fault RW 0 4.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Mode (Note 4-1) Default 100BASE-TX Half-Duplex 1 = 100 Mbps half-duplex capable 0 = No 100 Mbps half-duplex capability RO 0 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RO 0 10BASE-T Half-Duplex 1 = 10 Mbps half-duplex capable 0 = No 10 Mbps half-duplex capability RO 0 Selector Field [00001] = IEEE 802.3 RO 0_0001 RO 0000_0000_000 RO/LH 0 Address 5.7 5.6 5.5 5.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default Register 8h – Link Partner Next Page Ability Next Page 1 = Additional Next Page(s) will follow 0 = Last page RO 0 8.14 Acknowledge 1 = Successful receipt of link word 0 = No successful receipt of link word RO 0 8.13 Message Page 1 = Message page 0 = Unformatted page RO 0 8.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description Mode (Note 4-1) Default 1b.11 Link Partner Acknowledge Interrupt Enable 1 = Enable Link Partner Acknowledge Interrupt 0 = Disable Link Partner Acknowledge Interrupt RW 0 1b.10 Link Down Interrupt Enable 1= Enable Link Down Interrupt 0 = Disable Link Down Interrupt RW 0 1b.9 Remote Fault Interrupt Enable 1 = Enable Remote Fault Interrupt 0 = Disable Remote Fault Interrupt RW 0 1b.
KSZ8041NL/RNL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address 1e:6:0 Name Reserved Description — Mode (Note 4-1) Default — — Register 1Fh – PHY Control 2 HP_MDIX 0 = Auto MDI/MDI-X mode 1 = HP Auto MDI/MDI-X mode RW 1 1f:14 MDI/MDI-X Select When Auto MDI/MDI-X is disabled, 0 = MDI mode Transmit on TX+/- (pins 7, 6) and Receive on RX+/- (pins 5, 4) 1 = MDI-X mode Transmit on RX+/- (pins 5,4) and Receive on TX+/- (pins 7, 6) RW 0 1f:13 Pair Swap Disable 1 = Disable auto MDI/MDI-X 0 =
KSZ8041NL/RNL TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode (Note 4-1) Default 1f.1 Enable SQE test 1 = Enable SQE test 0 = Disable SQE test RW 0 1f.0 Disable Data Scrambling 1 = Disable scrambler 0 = Enable scrambler RW 0 Note 4-1 RW = Read/Write RO = Read only SC = Self-cleared LH = Latch high LL = Latch low 2017 Microchip Technology Inc.
KSZ8041NL/RNL 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings (Note 5-1) Supply Voltage (VDDPLL_1.8)...................................................................................................................... –0.5V to +2.4V Supply Voltage (VDDPLL_3.3, VDDPLL_3.3) .................................................................................................. –0.5V to +4.0V Input Voltage (all inputs).................................................................................
KSZ8041NL/RNL 6.0 ELECTRICAL CHARACTERISTICS TABLE 6-1: ELECTRICAL CHARACTERISTICS (Note 6-1, Note 6-2) Symbol Parameter Condition Min. Typ. Max. Units Supply Current IDD1 100BASE-TX Chip only (no transformer); Full-duplex traffic @ 100% utilization — 53.0 — mA IDD2 10BASE-T Chip only (no transformer); Full-duplex traffic @ 100% utilization — 38.0 — mA IDD3 Power-Saving Mode Ethernet cable disconnected (reg. 1F.10 = 1) — 32.
KSZ8041NL/RNL 7.0 TIMING DIAGRAMS 7.1 MII SQE Timing FIGURE 7-1: MII SQE TIMING (10BASE-T) t WL TXC tWH tP TXEN t SQE COL TABLE 7-1: tSQEP MII SQE TIMING (10BASE-T) PARAMETERS Timing Parameter Description Min. Typ. Max. Unit 400 — — ns 200 ns tP TXC Period tWL TXC Pulse Width Low — — tWH TXC Pulse Width High — 200 — tSQE COL (SQE) Delay After TXEN De-Asserted — 2.5 — us tSQEP COL (SQE) Pulse Duration — 1.0 — us 7.
KSZ8041NL/RNL TABLE 7-2: MII TRANSMIT TIMING (10BASE-T) PARAMETERS Timing Parameter Description Min. Typ. Max.
KSZ8041NL/RNL 7.4 MII Transmit Timing (100BASE-TX) FIGURE 7-4: MII TRANSMIT TIMING (100BASE-TX) t WL TXC t WH tHD2 tSU2 tP TXEN tHD1 tSU1 Data In TXD[3:0] tCRS2 tCRS1 CRS TABLE 7-4: MII TRANSMIT TIMING (100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ. Max.
KSZ8041NL/RNL 7.5 MII Receive Timing (100BASE-TX) FIGURE 7-5: MII RECEIVE TIMING (100BASE-TX) CRS t RLAT RXDV t OD RXD[3:0] RXER tWL RXC tWH tP TABLE 7-5: MII RECEIVE TIMING (100BASE-TX) PARAMETERS Timing Parameter Description Min. Typ Max.
KSZ8041NL/RNL 7.6 RMII Timing FIGURE 7-6: RMII TIMING – DATA RECEIVED FROM RMII FIGURE 7-7: RMII TIMING – DATA INPUT TO RMII Receive Timing tcyc REFCLK CRSDV RXD[1:0] tod TABLE 7-6: RMII TIMING PARAMETERS – KSZ8041NL Timing Parameter Description Min. Typ Max. Units tcyc Clock Cycle — 20 — ns t1 Setup Time 4 — — ns t2 Hold Time 2 — — ns tod Output Delay 3 — 9 ns Min. Typ Max.
KSZ8041NL/RNL 7.7 Auto-Negotiation Timing FIGURE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING Auto-Negotiation Fast Link Pulse (FLP) Timing FLP Burst FLP Burst TX+/TX- tFLPW tBTB TX+/TX- Clock Pulse Data Pulse tPW tPW Clock Pulse Data Pulse tCTD tCTC TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS Timing Parameter Description Min. Typ Max.
KSZ8041NL/RNL 7.8 MDC/MDIO Timing FIGURE 7-9: MDC/MDIO TIMING tP MDC tMD1 tMD2 Valid Data MDIO (PHY input) Valid Data tMD3 Valid Data MDIO (PHY output) TABLE 7-9: MDC/MDIO TIMING PARAMETERS Timing Parameter Description Min. Typ. Max.
KSZ8041NL/RNL 7.9 Power-Up/Reset Timing The KSZ8041NL/RNL reset timing requirement is summarized in Figure 7-10 and Figure 7-10. FIGURE 7-10: TABLE 7-10: POWER-UP/RESET TIMING POWER-UP/RESET TIMING PARAMETERS Parameters Description Min Max Units tVR Supply Voltage (VDDIO_3.3, VDDA_3.
KSZ8041NL/RNL 7.10 Reset Circuit The reset circuit in Figure 7-11 is recommended for powering up the KSZ8041NL/RNL if reset is triggered by the power supply. FIGURE 7-11: RECOMMENDED RESET CIRCUIT 3.3V D1: 1N4148 R 10k D1 KSZ8041NL RST# C 10µF Figure 7-12 shows a reset circuit recommended for applications where reset is driven by another device (for example, the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset.
KSZ8041NL/RNL 7.11 Reference Circuits for LED Strapping Pins The Figure 7-13 shows the reference circuits for pull-up, float, and pull-down on the LED1 and LED0 strapping pins. FIGURE 7-13: REFERENCE CIRCUITS FOR LED STRAPPING PINS 3.3V Pull-up 4.7kΩ 220Ω KSZ8041NL/RNL LED pin 3.3V Float 220Ω KSZ8041NL/RNL LED pin 3.3V Pull-down 220Ω KSZ8041NL/RNL LED pin 1kΩ 2017 Microchip Technology Inc.
KSZ8041NL/RNL 8.0 SELECTION OF ISOLATION TRANSFORMER A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode chokes is recommended for exceeding FCC requirements. Table 8-1 gives the recommended transformer characteristics. TABLE 8-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Condition 1 CT : 1 CT — Open-Circuit Inductance (minimum) 350 H 100 mV, 100 kHz, 8 mA Leakage Inductance (maximum) 0.
KSZ8041NL/RNL 9.0 SELECTION OF REFERENCE CRYSTAL TABLE 9-1: TYPICAL REFERENCE CRYSTAL CHARACTERISTICS Characteristics Value Units Frequency 25 MHz Frequency Tolerance (maximum) ±50 ppm Load Capacitance 20 pF Series Resistance 40 Ω 2017 Microchip Technology Inc.
KSZ8041NL/RNL 10.0 Note: PACKAGE OUTLINE & RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. FIGURE 10-1: 32-LEAD QFN 5X5 PACKAGE TITLE 32 LEAD QFN 5x5mm PACKAGE OUTLINE & RECOMMENDED LAND PATTERN DRAWING # QFN55-32LD-PL-1 DS00002245B-page 52 UNIT MM 2017 Microchip Technology Inc.
KSZ8041NL/RNL APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry Figure 10-1 Updated the 32-LEAD QFN 5X5 Package illustration. — Minor text changes throughout. ALL KSZ8041NL/RNL Datasheet initial conversion to Microchip DS00002245A. DS00002245B (11-17-17) DS00002245A (05-02-17) 2017 Microchip Technology Inc.
KSZ8041NL/RNL THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
KSZ8041NL/RNL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, for example, on pricing or delivery, refer to the factory or the listed sales office. PART NO.
KSZ8041NL/RNL NOTES: DS00002245B-page 56 2017 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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