Datasheet

 2017 Microchip Technology Inc. DS00002436B-page 53
KSZ8041TL/FTL/MLL
7.10 Reset Timing
The KSZ8041TL/FTL/MLL reset timing requirement is summarized in the following figure and table.
After the de-assertion of reset, it is recommended to wait a minimum of 100 µs before starting programming on the MIIM
(MDC/MDIO) Interface.
FIGURE 7-12: RESET TIMING
TABLE 7-10: RESET TIMING PARAMETERS
Parameter Description Min. Typ. Max. Units
t
SR
Stable supply voltage to reset high 10 — — ms
t
CS
Configuration setup time 5 — — ns
t
CH
Configuration hold time 5 — — ns
t
RC
Reset to strap-in pin output 6 — — ns
tsr
tcs tch
trc
Supply
Voltage
RST#
Strap-In
Value
Strap-In /
Output Pin