Datasheet

 2017 Microchip Technology Inc. DS00002436B-page 47
KSZ8041TL/FTL/MLL
7.4 MII Transmit Timing (100BASE-TX)
FIGURE 7-4: MII TRANSMIT TIMING (100BASE-TX)
TABLE 7-4: MII TRANSMIT TIMING (100BASE-TX) PARAMETERS
Parameter Description Min. Typ. Max. Units
t
P
TXC period — 40 — ns
t
WL
TXC pulse width low — 20 — ns
t
WH
TXC pulse width high — 20 — ns
t
SU1
TXD[3:0] setup to rising edge of TXC 10 — — ns
t
SU2
TXEN setup to rising edge of TXC 10 — — ns
t
HD1
TXD[3:0] hold from rising edge of TXC 0 — — ns
t
HD2
TXEN hold from rising edge of TXC 0 — — ns
t
CRS1
TXEN high to CRS asserted latency — 34 — ns
t
CRS2
TXEN low to CRS de-asserted latency — 33 — ns
TXC
TXEN
TXD[3:0]
CRS
DATA
IN
t
SU2
t
HD2
t
SU1
t
HD1
t
P
t
WH
t
WL
t
CRS1
t
CRS2