Datasheet
2017 Microchip Technology Inc. DS00002436B-page 45
KSZ8041TL/FTL/MLL
7.2 MII Transmit Timing (10BASE-T)
FIGURE 7-2: MII TRANSMIT TIMING (10BASE-T)
TABLE 7-2: MII TRANSMIT TIMING (10BASE-T) PARAMETERS
Symbol Parameter Min. Typ. Max. Units
t
P
TXC period — 400 —
t
WL
TXC pulse width low — 200 —
t
WH
TXC pulse width high — 200 —
t
SU1
TXD[3:0] setup to rising edge of TXC 10 — —
t
SU2
TXEN setup to rising edge of TXC 10 — —
t
HD1
TXD[3:0] hold from rising edge of TXC 0 — —
t
HD2
TXEN hold from rising edge of TXC 0 — —
t
CRS1
TXEN high to CRS asserted latency — 160 —
t
CRS2
TXEN low to CRS de-asserted latency — 510 —
TXC
t
HD2
t
SU2
TXEN
TXD[3:0]
t
SU1
t
HD1
CRS
t
CRS2
t
CRS1
t
WH
t
WL
t
P