Datasheet

 2017 Microchip Technology Inc. DS00002436B-page 25
KSZ8041TL/FTL/MLL
3.14.6 RECEIVE ERROR (RX_ER)
RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is
capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the
frame presently being transferred from the PHY.
RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on
the MAC.
3.14.7 COLLISION DETECTION
The MAC regenerates the COL signal of the MII from TX_EN and CRS_DV.
3.15 Serial MII (SMII) Data Interface (KSZ8041TL/FTL Only)
The Serial Media Independent Interface (SMII) is the lowest pin count Media Independent Interface (MII). It provides a
common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Supports 10 Mbps and 100 Mbps data rates.
• Uses 125 MHz reference clock provided by the MAC or the system board.
• Uses 12.5 MHz sync pulse provided by the MAC.
• Provides independent single-bit wide transmit and receive data paths for data and control information.
The KSZ8041TL/FTL is configured in SMII mode after it is power-up or reset with the following:
• A 125 MHz reference clock connected to CLOCK (pin 15).
• A 12.5 MHz sync pulse connected to SYNC (pin 36).
• CONFIG[2:0] (pins 27, 41, 40) set to ‘010’.
In SMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground.
3.16 SMII Signal Definition (KSZ8041TL/FTL Only)
The following table describes the SMII signals. Refer to SMII Specification for detailed information.
3.16.1 CLOCK REFERENCE (CLOCK)
CLOCK is sourced by the MAC or system board. It is a continuous 125 MHz clock that provides the timing reference for
SYNC, TX, and RX.
3.16.2 SYNC PULSE (SYNC)
SYNC is a 12.5 MHz synchronized pulse derived from CLOCK by the MAC. It is used to indicate the segment boundary
for each transmit data/control segment, or receive data/control segment. Each segment is comprised of ten bits.
SYNC is generated continuously by the MAC at every ten cycles of CLOCK.
3.16.3 TRANSMIT DATA AND CONTROL (TX)
TX provides transmit data and control information from MAC-to-PHY in 10-bit segments.
• In 10 Mbps mode, each segment is repeated ten times. Therefore, every ten segments represent a new byte of
data. The PHY can sample any one of every ten segments.
• In 100 Mbps mode, each segment represents a new byte of data.
TABLE 3-4: SMII SIGNAL DESCRIPTION
SMII Signal
Name
Direction with
Respect to PHY
Direction with
Respect to MAC
Description
CLOCK Input Input or Output 125 MHz clock reference for receive and transmit
data and control
SYNC Input Output 12.5 MHz sync pulse from MAC
TX Input Output Transmit Data and Control
RX Output Input Receive Data and Control