Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 24  2017 Microchip Technology Inc.
• Supports 10 Mbps and 100 Mbps data rates.
• Uses a single 50 MHz reference clock provided by the MAC or the system board.
• Provides independent 2-bit wide (di-bit) transmit and receive data paths.
• Contains two distinct groups of signals: one for transmission and the other for reception.
The KSZ8041TL/FTL is configured in RMII mode after it is power-up or reset with the following:
• A 50 MHz reference clock connected to REFCLK (pin 15).
• CONFIG[2:0] (pins 27, 41, 40) set to ‘001’.
In RMII mode, unused MII signals, TXD[3:2] (pins 39, 38), are tied to ground.
3.14 RMII Signal Definition (KSZ8041TL/FTL Only)
The following table describes the RMII signals. Refer to RMII Specification for detailed information.
3.14.1 REFERENCE CLOCK (REF_CLK)
REF_CLK is sourced by the MAC or system board. It is a continuous 50 MHz clock that provides the timing reference
for TX_EN, TXD[1:0], CRS_DV, RXD[1:0], and RX_ER.
3.14.2 TRANSMIT ENABLE (TX_EN)
TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] for transmission. It is asserted synchronously with the
first nibble of the preamble and remains asserted while all di-bits to be transmitted are presented on the RMII, and is
negated prior to the first REF_CLK following the final di-bit of a frame.
TX_EN transitions synchronously with respect to REF_CLK.
3.14.3 TRANSMIT DATA [1:0] (TXD[1:0])
TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are accepted for
transmission by the PHY. TXD[1:0] is “00” to indicate idle when TX_EN is de-asserted. Values other than “00” on
TXD[1:0] while TX_EN is de-asserted are ignored by the PHY.
3.14.4 CARRIER SENSE/RECEIVE DATA VALID (CRS_DV)
CRS_DV is asserted by the PHY when the receive medium is non-idle. It is asserted asynchronously on detection of
carrier. This is when squelch is passed in 10 Mbps mode, and when two non-contiguous zeroes in 10 bits are detected
in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.
So long as carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered di-bit of
the frame through the final recovered di-bit, and it is negated prior to the first REF_CLK that follows the final di-bit. The
data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchro-
nous relative to REF_CLK, the data on RXD[1:0] is “00” until proper receive signal decoding takes place.
3.14.5 RECEIVE DATA [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] trans-
fers two bits of recovered data from the PHY. RXD[1:0] is “00” to indicate idle when CRS_DV is de-asserted. Values
other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC.
TABLE 3-3: RMII SIGNAL DEFINITIONS
RMII Signal
Name
Direction with
Respect to PHY
Direction with
Respect to MAC
Description
REF_CLK Input Input or Output Synchronous 50 MHz clock reference for receive,
transmit and control interface
TX_EN Input Output Transmit Enable
TXD[1:0] Input Output Transmit Data [1:0]
CRS_DV Output Input Carrier Sense/Receive Data Valid
RXD[1:0] Output Input Receive Data [1:0]
RX_ER Output Input or not required Receive Error