Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 22  2017 Microchip Technology Inc.
3.10 Interrupt (INTRP)
INTRP (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status
update to the KSZ8041TL/FTL/MLL PHY register. Bits[15:8] of register 1Bh are the interrupt control bits, and are used
to enable and disable the conditions for asserting the INTRP signal. Bits[7:0] of register 1Bh are the interrupt status bits,
and are used to indicate which interrupt conditions have occurred. The interrupt status bits are cleared after reading
register 1Bh.
Bit 9 of register 1Fh sets the interrupt level to active-high or active-low.
3.11 MII Data Interface
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3 Specification. It provides a common
interface between physical layer and MAC layer devices, and has the following key characteristics:
• Supports 10 Mbps and 100 Mbps data rates.
• Uses a 25 MHz reference clock, sourced by the PHY.
• Provides independent 4-bit wide (nibble) transmit and receive data paths.
• Contains two distinct groups of signals: one for transmission and the other for reception.
By default, the KSZ8041TL/FTL/MLL is configured to MII mode after it is power-up or reset with the following:
• A 25 MHz crystal connected to XI, XO (pins 15, 14), or an external 25 MHz clock source (oscillator) connected to
XI.
• CONFIG[2:0] (pins 27, 41, 40) set to ‘000’ (default setting).
3.12 MII Signal Definition
The following table describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
3.12.1 TRANSMIT CLOCK (TXC)
TXC is sourced by the PHY. It is a continuous clock that provides the timing reference for TXEN and TXD[3:0].
TXC is 2.5 MHz for 10 Mbps operation and 25 MHz for 100 Mbps operation.
TABLE 3-1: MII MANAGEMENT FRAME FORMAT
—Preamble
Start
of
Frame
R/W
OP
Code
PHY
Address
Bits[4:0]
REG
Address
Bits[4:0]
TA Data Bits [15:0] Idle
Read 32 1’s 01 10 00AAA RRRRR Z0 DDDDDDDD_DDDDDDDD Z
Write 32 1’s 01 01 00AAA RRRRR 10 DDDDDDDD_DDDDDDDD Z
TABLE 3-2: MII SIGNAL DEFINITIONS
MII Signal
Name
Direction with
Respect to PHY
Direction with
Respect to MAC
Description
TXC Output Input Transmit Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
TXEN Input Output Transmit Enable
TXD[3:0] Input Output Transmit Data [3:0]
RXC Output Input Receive Clock
(2.5 MHz for 10 Mbps; 25 MHz for 100 Mbps)
RXDV Output Input Receive Data Valid
RXD[3:0] Output Input Receive Data [3:0]
RXER Output Input or not required Receive Error
CRS Output Input Carrier Sense
COL Output Input Collision Detection