Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 16  2017 Microchip Technology Inc.
14 XO O
Crystal feedback
This pin is used only when a 25 MHz crystal is used.
This pin is a no connect if oscillator or external clock source is used.
15 XI I
Crystal/Oscillator/External Clock Input
25 MHz ±50 ppm
16 REXT I/O
Set physical transmit output current
Connect a 6.49 k resistor in parallel with a 100 pF capacitor to ground on this
pin. See KSZ8041MLL reference schematic.
17 GND GND Ground
18 MDIO I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7 k pull-up resistor.
19 MDC I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
20
RXD3/
PHYAD0
Ipu/O
MII Mode: Receive Data Output[3](Note 2-2)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[0] during
power-up/reset. See Table 2-4 for details.
21
RXD2/
PHYAD1
Ipd/O
MII Mode: Receive Data Output[2](Note 2-2)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[1] during
power-up/reset. See Table 2-4 for details.
22
RXD1/
PHYAD2
Ipd/O
MII Mode: Receive Data Output[1](Note 2-2)
Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during
power-up/reset. See Table 2-4 for details.
23
RXD0/
DUPLEX
Ipu/O
MII Mode: Receive Data Output[0](Note 2-2)
Config Mode: Latched as DUPLEX (register 0h, bit 8) during power-up/reset.
See Table 2-4 for details.
24 GND GND Ground
25 VDDIO_3.3 P 3.3V digital V
DD
26 VDDIO_3.3 P 3.3V digital V
DD
27
RXDV/
CONFIG2
Ipd/O
MII Mode: Receive Data Valid Output
Config. Mode: The pull-up/pull-down value is latched as CONFIG2 during
power-up/reset. See Table 2-4 for details.
28 RXC O MII Receive Clock Output
29 RXER/ISO Ipd/O
MII Mode: Receive Error Output
Config. Mode: The pull-up/pull-down value is latched as ISOLATE during
power-up/reset. See Table 2-4 for details.
30 GND GND Ground
31 VDD_1.8 P 1.8V digital V
DD
32 INTRP Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active-low (default) or active-high.
33 TXC I/O MII Transmit Clock Output
34 TXEN I MII Transmit Enable Input
35 TXD0 I MII Transmit Data Input[0](Note 2-3)
36 TXD1 I MII Transmit Data Input[1](Note 2-3)
37 GND GND Ground
38 TXD2 I MII Transmit Data Input[2](Note 2-3)
39 TXD3 I MII Transmit Data Input[3](Note 2-3)
TABLE 2-3: SIGNALS FOR KSZ8041MLL (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
Description