Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 14  2017 Microchip Technology Inc.
Note 2-1 Ipu/O = Input with internal pull-up (40 k ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40 k ±30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In
this case, it is recommended to add 1 k pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
23 DUPLEX Ipu/O
DUPLEX mode
Pull-up (default) = Half-Duplex
Pull-down = Full-Duplex
During power-up/reset, this pin value is latched into register 0h bit 8 as the
Duplex Mode.
42
(TL)
NWAYEN Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up/reset, this pin value is latched into register 0h bit 12.
42
(FTL)
NWAYEN Ipu/O
If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up/reset, this pin value is latched into register 0h bit 12.
If fiber mode (FXEN=1), this pin configuration is always strapped to disable
Auto-Negotiation.
TABLE 2-2: STRAP-IN OPTIONS KSZ8041TL/FTL (CONTINUED)
Pin
Number
Pin Name
Type
Note 2-1
Description