Datasheet

 2017 Microchip Technology Inc. DS00002436B-page 13
KSZ8041TL/FTL/MLL
Note 2-4 SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100 MBit mode,
each segment represents a new byte of data. In 10 MBit mode, each segment is repeated ten times;
therefore, every ten segments represent a new byte of data. The MAC can sample any one of every
10 segments in 10 MBit mode.
Note 2-5 MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0]
presents valid data from the MAC through the MII. TXD[3..0] has no effect when TXEN is de-
asserted.
Note 2-6 RMII Tx Mode: The TXD[1:0] bits are synchronous with REF_CLK. For each clock period in which
TX_EN is asserted, two bits of data are received by the PHY from the MAC.
Note 2-7 SMII Tx Mode: Transmit data and control information are received in 10 bit segments. In 100 MBit
mode, each segment represents a new byte of data. In 10 MBit mode, each segment is repeated ten
times; therefore, every ten segments represent a new byte of data. The PHY can sample any one of
every 10 segments in 10 MBit mode.
TABLE 2-2: STRAP-IN OPTIONS KSZ8041TL/FTL
Pin
Number
Pin Name
Type
Note 2-1
Description
22
21
20
PHYAD2
PHYAD1
PHYAD0
Ipd/O
Ipd/O
Ipu/O
The PHY Address is latched at power-up/reset and is configurable to any
value from 1 to 7.
The default PHY Address is 00001.
PHY Address bits [4:3] are always set to ‘00’.
27
41
40
CONFIG2
CONFIG1
CONFIG0
Ipd/O
Ipd/O
Ipd/O
The CONFIG[2:0] strap-in pins are latched at power-up/reset and are
defined as follows:
CONFIG[2:0] Mode
000 MII (default)
001 RMII
010 SMII
011 Reserved - not used
100 MII 100 Mbps Preamble Restore
101 RMII back-to-back
110 MII back-to-back
111 Reserved - not used
29 ISO Ipd/O
ISOLATE mode
Pull-up = Enable
Pull-down (default) = Disable
During power-up/reset, this pin value is latched into register 0h bit 10.
43
(TL)
SPEED Ipu/O
SPEED mode
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
During power-up/reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Adver-
tisement) as the Speed capability support.
43
(FTL)
SPEED
Ipu/O
If copper mode (FXEN=0), pin strap-in is SPEED mode.
Pull-up (default) = 100 Mbps
Pull-down = 10 Mbps
During power-up/reset, this pin value is latched into register 0h bit 13 as the
Speed Select, and also is latched into register 4h (Auto-Negotiation Adver-
tisement) as the Speed capability support.
no FEF
If fiber mode (FXEN=1), pin strap-in is no FEF.
Pull-up (default) = Enable Far-End Fault
Pull-down = Disable Far-End Fault
This pin value is latched during power-up/reset.