Datasheet

KSZ8041TL/FTL/MLL
DS00002436B-page 12  2017 Microchip Technology Inc.
Note 2-1 P = power supply
GND = ground
I = input
O = output
I/O = bi-directional
Ipu/O = Input with internal pull-up (40 k ±30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40 k ±30%) during power-up/reset; output pin otherwise.
Ipu = Input with internal pull-up. (40 k ±30%)
Ipd = Input with internal pull-down. (40 k ±30%)
Opu = Output with internal pull-up. (40 k ±30%)
Note 2-2 MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0]
presents valid data to MAC through the MII. RXD[3..0] is invalid when RXDV is de-asserted.
Note 2-3 RMII Rx Mode: The RXD[1:0] bits are synchronous with REF_CLK. For each clock period in which
CRS_DV is asserted, two bits of recovered data are sent from the PHY.
43
(FTL)
LED1/SPEED
no FEF
Ipu/O
LED Output: Programmable LED1 Output
Config. Mode: If copper mode (FXEN=0), latched as SPEED (register 0h, bit
13) during power-up/reset. If fiber mode (FXEN=1), latched as no FEF (no
Far-End Fault) during power-up/reset. See Table 2-2 for details.
The LED1 pin is programmable via register 1Eh bits [15:14], and is defined as
follows:
LED mode = [00]
Speed Pin State LED Definition
10BT High OFF
100BT Low ON
LED mode = [01]
Activity Pin State LED Definition
No Activity High OFF
Activity Toggle Blinking
LED Mode = [10]: Reserved
LED Mode = [11]: Reserved
44 NC — No connect
45 NC — No connect
46 NC — No connect
47 RST# I Chip reset (active-low)
48
(TL)
NC — No connect
48
(FTL)
FXSD/FXEN Ipd
FXSD: Signal Detect for 100BASE-FX fiber mode
FXEN: Fiber Enable for 100BASE-FX fiber mode
If FXEN=0, fiber mode is disabled. PHY is in copper mode. The default is “0”.
See “100BASE-FX Operation” section for details.
TABLE 2-1: SIGNALS FOR KSZ8041TL/FTL (CONTINUED)
Pin
Number
Pin Name
Type
(Note
2-1)
Description