KSZ8041TL/FTL/MLL 10BASE-T/100BASE-TX/100BASE-FX Physical Layer Transceiver Features Applications • Single-Chip 10BASE-T/100BASE-TX/100BASEFX Physical Layer Solution • Fully Compliant with IEEE 802.
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KSZ8041TL/FTL/MLL Table of Contents 1.0 Introduction ..................................................................................................................................................................................... 4 2.0 Pin Description and Configuration .................................................................................................................................................. 6 3.0 Functional Description .............................................................
KSZ8041TL/FTL/MLL 1.0 INTRODUCTION 1.1 General Description The KSZ8041TL is a single supply 10BASE-T/100BASE-TX Physical Layer Transceiver that provides MII/RMII/SMII interfaces to transmit and receive data. It utilizes a unique mixed-signal design to extend signaling distance while reducing power consumption. HP Auto MDI/MDI-X provides the most robust solution for eliminating the need to differentiate between crossover and straight-through cables.
KSZ8041TL/FTL/MLL FIGURE 1-2: TX+ TX- SYSTEM BLOCK DIAGRAM, KSZ8041MLL 10/100 Pulse Transmitter NRZ/NRZI MLT3 Encoder 4B/5B Encoder MDC MDIO Scrambler Parallel /Serial TXC TXEN TXD3 TXD2 TXD1 TXD0 Shaper Parallel /Serial Manchester Encoder REXT Adaptive EQ Base Line Wander Correction MLT3 Decoder RX+ RX- Clock Recovery 4B/5B Decoder Descrambler Serial/Parallel MII NRZI/NRZ Auto Negotiation RXC RXDV RXD3 RXD2 RXD1 RXD0 RXER CRS COL 10BASE-T Manchester Decoder Receiver Serial/Parallel INT
KSZ8041TL/FTL/MLL PIN DESCRIPTION AND CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 RST# NC NC NC LED1 / SPEED LED0 / NWAYEN CRS / CONFIG1 COL / CONFIG0 TXD3 TXD2 GND KSZ8041TL 48-PIN TQFP ASSIGNMENT, (TOP VIEW) NC FIGURE 2-1: 1 GND TXD1 / TXD[1] / SYNC 36 2 GND TXD0 / TXD[0] / TX 35 3 GND TXEN / TX_EN 34 4 VDDA_1.8 TXC 33 5 VDDA_1.8 INTRP 32 6 V1.8_OUT VDD_1.8 31 7 VDDA_3.3 GND 30 8 VDDA_3.
KSZ8041TL/FTL/MLL 48 47 46 45 44 43 42 41 40 39 38 37 RST# NC NC NC LED1 / SPEED / no FEF LED0 / NWAYEN CRS / CONFIG1 COL / CONFIG0 TXD3 TXD2 GND KSZ8041FTL 48-PIN TQFP ASSIGNMENT, (TOP VIEW) FXSD / FXEN FIGURE 2-2: TXD1 / TXD[1] / SYNC 36 GND TXD0 / TXD[0] / TX 35 3 GND TXEN / TX_EN 34 4 VDDA_1.8 TXC 33 5 VDDA_1.8 INTRP 32 6 V1.8_OUT VDD_1.8 31 7 VDDA_3.3 GND 30 8 VDDA_3.
KSZ8041TL/FTL/MLL TABLE 2-1: SIGNALS FOR KSZ8041TL/FTL Pin Number Pin Name Type (Note 2-1) 1 GND GND Ground 2 GND GND Ground 3 GND GND Ground 4 VDDA_1.8 P 1.8V analog VDD 5 VDDA_1.8 P 1.8V analog VDD 6 V1.8_OUT P 1.8V output voltage from chip 7 VDDA_3.3 P 3.3V analog VDD 8 VDDA_3.3 P 3.
KSZ8041TL/FTL/MLL TABLE 2-1: SIGNALS FOR KSZ8041TL/FTL (CONTINUED) Type (Note 2-1) Description Ipd/O MII Mode: Receive Data Output[1](Note 2-2) RMII Mode: Receive Data Output[1](Note 2-3) Config. Mode: The pull-up/pull-down value is latched as PHYADDR[2] during power-up/reset. See Table 2-2 for details. 23 RXD0/ RXD[0]/ RX DUPLEX Ipu/O MII Mode: Receive Data Output[0](Note 2-2) RMII Mode: Receive Data Output[0](Note 2-3) SMII Mode: Receive Data and Control(Note 2-4) Config.
KSZ8041TL/FTL/MLL TABLE 2-1: SIGNALS FOR KSZ8041TL/FTL (CONTINUED) Pin Number Pin Name Type (Note 2-1) 40 COL/ CONFIG0 Ipd/O MII Mode: Collision Detect Output Config. Mode: The pull-up/pull-down value is latched as CONFIG0 during power-up/reset. See Table 2-2 for details. 41 CRS/ CONFIG1 Ipd/O MII Mode: Carrier Sense Output Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up/reset. See Table 2-2 for details. Description LED Output: Programmable LED0 Output Config.
KSZ8041TL/FTL/MLL TABLE 2-1: Pin Number SIGNALS FOR KSZ8041TL/FTL (CONTINUED) Pin Name Type (Note 2-1) Description LED Output: Programmable LED0 Output Config. Mode: If copper mode (FXEN=0), latched as Auto-Negotiation Enable (register 0h, bit 12) during power-up/reset. If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-Negotiation. See Table 2-2 for details.
KSZ8041TL/FTL/MLL TABLE 2-1: Pin Number SIGNALS FOR KSZ8041TL/FTL (CONTINUED) Pin Name Type (Note 2-1) Description LED Output: Programmable LED1 Output Config. Mode: If copper mode (FXEN=0), latched as SPEED (register 0h, bit 13) during power-up/reset. If fiber mode (FXEN=1), latched as no FEF (no Far-End Fault) during power-up/reset. See Table 2-2 for details.
KSZ8041TL/FTL/MLL Note 2-4 SMII Rx Mode: Receive data and control information are sent in 10 bit segments. In 100 MBit mode, each segment represents a new byte of data. In 10 MBit mode, each segment is repeated ten times; therefore, every ten segments represent a new byte of data. The MAC can sample any one of every 10 segments in 10 MBit mode. Note 2-5 MII Tx Mode: The TXD[3..0] bits are synchronous with TXCLK. When TXEN is asserted, TXD[3..0] presents valid data from the MAC through the MII. TXD[3..
KSZ8041TL/FTL/MLL TABLE 2-2: Pin Number 23 42 (TL) 42 (FTL) STRAP-IN OPTIONS KSZ8041TL/FTL (CONTINUED) Pin Name DUPLEX NWAYEN NWAYEN Type Note 2-1 Description Ipu/O DUPLEX mode Pull-up (default) = Half-Duplex Pull-down = Full-Duplex During power-up/reset, this pin value is latched into register 0h bit 8 as the Duplex Mode.
KSZ8041TL/FTL/MLL TABLE 2-3: 48 47 46 45 44 43 42 41 40 39 38 37 RST# NC NC NC LED1 / SPEED LED0 / NWAYEN CRS / CONFIG1 COL / CONFIG0 TXD3 TXD2 GND KSZ8041MLL 48-PIN TQFP ASSIGNMENT, (TOP VIEW) NC FIGURE 2-3: 1 GND TXD1 36 2 GND TXD0 35 3 GND TXEN 34 4 VDDA_1.8 TXC 33 5 VDDA_1.8 INTRP 32 6 V1.8_OUT VDD_1.8 31 7 VDDA_3.3 GND 30 8 VDDA_3.3 RXER / ISO 29 9 RX- RXC 28 10 RX+ RXDV / CONFIG2 27 11 TX- VDDIO_3.3 26 12 TX+ VDDIO_3.
KSZ8041TL/FTL/MLL TABLE 2-3: SIGNALS FOR KSZ8041MLL (CONTINUED) Pin Number Pin Name Type Note 2-1 14 XO O Crystal feedback This pin is used only when a 25 MHz crystal is used. This pin is a no connect if oscillator or external clock source is used. 15 XI I Crystal/Oscillator/External Clock Input 25 MHz ±50 ppm 16 REXT I/O 17 GND GND 18 MDIO I/O Management Interface (MII) Data I/O This pin requires an external 4.7 kΩ pull-up resistor.
KSZ8041TL/FTL/MLL TABLE 2-3: SIGNALS FOR KSZ8041MLL (CONTINUED) Pin Number Pin Name Type Note 2-1 40 COL/ CONFIG0 Ipd/O MII Mode: Collision Detect Output Config. Mode: The pull-up/pull-down value is latched as CONFIG0 during power-up/reset. See Table 2-4 for details. 41 CRS/ CONFIG1 Ipd/O MII Mode: Carrier Sense Output Config. Mode: The pull-up/pull-down value is latched as CONFIG1 during power-up/reset. See Table 2-4 for details. Description LED Output: Programmable LED0 Output Config.
KSZ8041TL/FTL/MLL Ipu/O = Input with internal pull-up (40 kΩ ±30%) during power-up/reset; output pin otherwise. Ipd/O = Input with internal pull-down (40 kΩ ±30%) during power-up/reset; output pin otherwise. Ipu = Input with internal pull-up. (40 kΩ ±30%) Ipd = Input with internal pull-down. (40 kΩ ±30%) Opu = Output with internal pull-up. (40 kΩ ±30%) Note 2-2 MII Rx Mode: The RXD[3..0] bits are synchronous with RXCLK. When RXDV is asserted, RXD[3..0] presents valid data to MAC through the MII. RXD[3..
KSZ8041TL/FTL/MLL 3.0 FUNCTIONAL DESCRIPTION The KSZ8041TL is a single 3.3V supply Fast Ethernet transceiver. It is fully compliant with the IEEE 802.3u specification. On the media side, the KSZ8041TL supports 10BASE-T and 100BASE-TX with HP auto MDI/MDI-X for reliable detection of and correction for straight-through and crossover cables. The KSZ8041TL offers a choice of MII, RMII, or SMII data interface connection to a MAC processor.
KSZ8041TL/FTL/MLL 3.6 10BASE-T Receive On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to prevent noise at the RX+ and RX– inputs from falsely trigger the decoder.
KSZ8041TL/FTL/MLL FIGURE 3-1: AUTO-NEGOTIATION FLOW CHART START AUTO-NEGOTIATION FORCE LINK SETTING NO PARALLEL OPERATION YES BYPASS AUTO-NEGOTIATION AND SET LINK MODE ATTEMPT AUTONEGOTIATION LISTEN FOR 100BASE-TX IDLES LISTEN FOR 10BASE-T LINK PULSES NO JOIN FLOW LINK MODE SET? YES LINK MODE SET 3.9 MII Management (MIIM) Interface The KSZ8041TL/FTL/MLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data Input/Output (MDIO) Interface.
KSZ8041TL/FTL/MLL TABLE 3-1: MII MANAGEMENT FRAME FORMAT Start R/W of OP Frame Code — Preamble Read 32 1’s 01 Write 32 1’s 01 3.10 PHY Address Bits[4:0] REG Address Bits[4:0] TA 10 00AAA RRRRR 01 00AAA RRRRR Data Bits [15:0] Idle Z0 DDDDDDDD_DDDDDDDD Z 10 DDDDDDDD_DDDDDDDD Z Interrupt (INTRP) INTRP (pin 32) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the KSZ8041TL/FTL/MLL PHY register.
KSZ8041TL/FTL/MLL 3.12.2 TRANSMIT ENABLE (TXEN) TXEN indicates the MAC is presenting nibbles on TXD[3:0] for transmission. It is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the MII, and is negated prior to the first TXC following the final nibble of a frame. TXEN transitions synchronously with respect to TXC. 3.12.3 TRANSMIT DATA [3:0] (TXD[3:0]) TXD[3:0] transitions synchronously with respect to TXC.
KSZ8041TL/FTL/MLL • • • • Supports 10 Mbps and 100 Mbps data rates. Uses a single 50 MHz reference clock provided by the MAC or the system board. Provides independent 2-bit wide (di-bit) transmit and receive data paths. Contains two distinct groups of signals: one for transmission and the other for reception. The KSZ8041TL/FTL is configured in RMII mode after it is power-up or reset with the following: • A 50 MHz reference clock connected to REFCLK (pin 15). • CONFIG[2:0] (pins 27, 41, 40) set to ‘001’.
KSZ8041TL/FTL/MLL 3.14.6 RECEIVE ERROR (RX_ER) RX_ER is asserted for one or more REF_CLK periods to indicate that a Symbol Error (e.g. a coding error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RX_ER has no effect on the MAC. 3.14.
KSZ8041TL/FTL/MLL FIGURE 3-2: SMII TRANSMIT DATA/CONTROL SEGMENT CLOCK SYNC TX TX_ER TABLE 3-5: TX_EN TXD0 TXD1 TXD2 TXD3 TXD5 TXD6 TXD7 SMII TX BIT DESCRIPTION SMII TX Bit Description TX_ER Transmit Error TX_EN Transmit Enable TXD[0:7] TABLE 3-6: TXD4 Encoded Data See Table 3-6.
KSZ8041TL/FTL/MLL FIGURE 3-3: SMII RECEIVE DATA/CONTROL SEGMENT CLOCK SYNC RX CRS TABLE 3-7: RX_DV RXD0 RXD1 RXD2 RXD3 RXD5 RXD6 RXD7 SMII RX BIT DESCRIPTION SMII RX Bit Description CRS Carrier Sense RX_DV Receive Data Valid RXD[0:7] TABLE 3-8: RXD4 Encoded Data See Table 3-8.
KSZ8041TL/FTL/MLL TABLE 3-9: MDI/MDI-X PIN DEFINITION MDI 3.17.1 MDI-X RJ-45 Pin Signal RJ-45 Pin Signal 1 2 TD+ 1 RD+ TD– 2 RD– 3 6 RD+ 3 TD+ RD– 6 TD– STRAIGHT CABLE A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-4 depicts a typical straight cable connection between a network interface card (NIC) and a switch, or hub (MDI-X).
KSZ8041TL/FTL/MLL 3.17.2 CROSSOVER CABLE A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device. Figure 3-5 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
KSZ8041TL/FTL/MLL 4. 5. Wait (poll) for register 1Dh bit 15 to return a ‘0’, indicating cable diagnostic test is completed. Read cable diagnostic test results in register 1Dh bits [14:13]. The results are as follows: 00 = Valid test, normal condition 01 = Valid test, open circuit in cable 10 = Valid test, short circuit in cable 11 = Invalid test, cable diagnostic test failed The ‘11’ case, invalid test, occurs if the KSZ8041TL/FTL/MLL is unable to shut down the link partner.
KSZ8041TL/FTL/MLL FIGURE 3-7: 50 MHZ OSCILLATOR REFERENCE CLOCK FOR RMII MODE REFCLK 50MHz OSC ±50ppm NC XO For the KSZ8041TL/FTL, the following figure illustrates how to connect the 125 MHz oscillator reference clock for SMII mode. FIGURE 3-8: 125 MHZ OSCILLATOR REFERENCE CLOCK FOR SMII MODE CLOCK 125MHz OSC ±100ppm 3.21 NC XO Reference Circuit for Power and Ground Connections The KSZ8041TL/FTL/MLL is a single 3.3V supply device with a built-in 1.8V low noise regulator.
KSZ8041TL/FTL/MLL FIGURE 3-9: KSZ8041TL/FTL/MLL POWER AND GROUND CONNECTIONS 1μF Ferrite Bead VIN 7 8 22μF VDDA_3.3 0.1μF V1.8_OUT 6 VOUT 1.8V Low Noise Regulator (integrated) Ferrite Bead VDD_1.8 31 0.1μF 0.1μF 25 3.3V 4 VDDIO_3.3 22μF 0.1μF 0.1μF KSZ8041TL/FTL/MLL 0.1μF GND 1 TABLE 3-10: Ferrite Bead VDDA_1.8 5 26 2 3 17 30 37 KSZ8041TL/FTL/MLL POWER PIN DESCRIPTION Power Pin Pin Number Pin Type V1.8_OUT 6 Output VDD_1.8 31 Input Connect to V1.
KSZ8041TL/FTL/MLL TABLE 3-11: COPPER AND FIBER MODE SELECTION FXSD Input Voltage Mode Less than 0.2V Copper mode Greater than 1V, but less than 1.8V Fiber mode No signal detected Far-End Fault generated (if enabled) Greater than 2.2V Fiber mode Signal detected To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD (signal detect) output voltage swing to match the FXSD pin’s input voltage threshold.
KSZ8041TL/FTL/MLL TABLE 3-12: MII SIGNAL CONNECTION FOR MII BACK-TO-BACK MODE KSZ8041MLL (100BASE-TX copper) KSZ8041TL (100BASE-TX copper) KSZ8041FTL (100BASE-FX fiber) KSZ8041MLL (100BASE-TX copper) KSZ8041TL (100BASE-TX copper) Pin Name Pin Number Pin Type Pin Name Pin Number Pin Type RXC 28 Output TXC 33 Input RXDV 27 Output TXEN 34 Input RXD3 20 Output TXD3 39 Input RXD2 21 Output TXD2 38 Input RXD1 22 Output TXD1 36 Input RXD0 23 Output TXD0 35 Input TXC 33
KSZ8041TL/FTL/MLL 4.0 REGISTER DESCRIPTIONS 4.1 Register Map TABLE 4-1: REGISTER MAP Register Number (Hex) 0h Basic Control 1h Basic Status 2h PHY Identifier 1 3h PHY Identifier 2 4h Auto-Negotiation Advertisement 5h Auto-Negotiation Link Partner Ability 6h Auto-Negotiation Expansion 7h Auto-Negotiation Next Page 8h Link Partner Next Page Ability 9h – 13h Reserved 14h MII Control 15h RXER Counter 16h – 1Ah 4.
KSZ8041TL/FTL/MLL TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Name Description 0.10 Isolate 1 = Electrical isolation of PHY from MII and TX+/ TX– 0 = Normal operation 0.9 Restart AutoNegotiation 0.8 Duplex Mode 0.7 1 = Restart auto-negotiation process 0 = Normal operation. This bit is self-cleared after a ‘1’ is written to it. Mode Default Note 4-1 RW RW/SC Set by ISO strapping pin. See Table 2-2 for details.
KSZ8041TL/FTL/MLL TABLE 4-2: Address REGISTER DESCRIPTIONS (CONTINUED) Name Description Mode Default Note 4-1 Register 3h – PHY Identifier 2 3.15:10 PHY ID Number Assigned to the 19th through 24th bits of the Organizationally Unique Identifier (OUI). Kendin Communication’s OUI is 0010A1 (hex). RO 0001_01 3.9:4 Model Number Six bit manufacturer’s model number. RO 01_0001 3.3:0 Revision Number Four bit manufacturer’s revision number.
KSZ8041TL/FTL/MLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Name 5.8 100BASETX FullDuplex 1 = 100 Mbps full-duplex capable 0 = No 100 Mbps full-duplex capability RO 0 5.7 100BASETX HalfDuplex 1 = 100 Mbps half-duplex capable 0 = No 100 Mbps half-duplex capability RO 0 5.6 10BASE-T Full-Duplex 1 = 10 Mbps full-duplex capable 0 = No 10 Mbps full-duplex capability RO 0 5.
KSZ8041TL/FTL/MLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name 8.12 Acknowledge2 8.11 Toggle 8.10:0 Message Field Description Mode Default Note 4-1 1 = Able to act on the information 0 = Not able to act on the information RO 0 1 = Previous value of transmitted link code word equal to logic zero 0 = Previous value of transmitted link code word equal to logic one RO 0 — RO 000_0000_0000 — RO 0000_0000 RW 0 or 1 (if CONFIG[2:0] = 100) See Table 2-2 for details.
KSZ8041TL/FTL/MLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description 1B.8 Link Up Interrupt Enable 1 = Enable Link Up Interrupt 0 = Disable Link Up Interrupt 1B.7 Jabber Interrupt 1B.6 1B.5 Mode Default Note 4-1 RW 0 1 = Jabber occurred 0 = Jabber did not occur RO/SC 0 Receive Error Interrupt 1 = Receive Error occurred 0 = Receive Error did not occur RO/SC 0 Page Receive Interrupt 1 = Page Receive occurred 0 = Page Receive did not occur RO/SC 0 1B.
KSZ8041TL/FTL/MLL TABLE 4-2: REGISTER DESCRIPTIONS (CONTINUED) Address Name Description 1E.7 Remote Loopback 0 = Normal mode 1 = Remote (analog) loopback is enable 1E.6:0 Reserved — Mode Default Note 4-1 RW 0 — — Register 1Fh – PHY Control 2 HP_MDIX 0 = Microchip Auto MDI/MDI-X mode 1 = HP Auto MDI/MDI-X mode RW 1 1F.
KSZ8041TL/FTL/MLL 5.0 OPERATIONAL CHARACTERISTICS 5.1 Absolute Maximum Ratings* Supply Voltage (VDD_1.8, VDDA_1.8, V1.8_OUT)........................................................................................... –0.5V to +2.4V Supply Voltage (VDDIO_3.3, VDDA_3.3)........................................................................................................ –0.5V to +4.0V Input Voltage (All Inputs) ..............................................................................................
KSZ8041TL/FTL/MLL 6.0 ELECTRICAL CHARACTERISTICS TA = 25°C. Specification is for packaged product only. TABLE 6-1: ELECTRICAL CHARACTERISTICS Parameters Symbol Min. Typ. Max. Units Note 100BASE-TX IDD1 — 53.0 58.3 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization 10BASE-T IDD2 — 38.0 41.8 mA Chip only (no transformer); Full-duplex traffic @ 100% utilization Power Saving Mode IDD3 — 32.0 35.2 mA Ethernet cable disconnected (reg. 1F.
KSZ8041TL/FTL/MLL 7.0 TIMING SPECIFICATIONS 7.1 MII SQE Timing (10BASE-T) FIGURE 7-1: MII SQE TIMING (10BASE-T) tWL TXC tWH tP TXEN tSQE COL TABLE 7-1: tSQEP MII SQE TIMING (10BASE-T) PARAMETERS Symbol Parameter Min. Typ. Max. Units tP TXC period — 400 — ns tWL TXC pulse width low — 200 — ns tWH TXC pulse width high — 200 — ns tSQE COL (SQE) delay after TXEN de-asserted — 2.5 — µs tSQEP COL (SQE) pulse duration — 1.
KSZ8041TL/FTL/MLL 7.2 MII Transmit Timing (10BASE-T) FIGURE 7-2: MII TRANSMIT TIMING (10BASE-T) tP tWL TXC TXEN TXD[3:0] tWH tHD2 tSU2 tSU1 tCRS1 CRS TABLE 7-2: tHD1 tCRS2 MII TRANSMIT TIMING (10BASE-T) PARAMETERS Symbol Parameter Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.3 MII Receive Timing (10BASE-T) FIGURE 7-3: MII RECEIVE TIMING (10BASE-T) CRS tRLAT RXDV tOD RXD[3:0] RXER tP tWL RXC TABLE 7-3: tWH MII RECEIVE TIMING (10BASE-T) PARAMETERS Parameter Description Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.4 MII Transmit Timing (100BASE-TX) FIGURE 7-4: MII TRANSMIT TIMING (100BASE-TX) tWL TXC tWH tHD2 tSU2 tP TXEN tHD1 tSU1 TXD[3:0] DATA IN tCRS2 CRS TABLE 7-4: tCRS1 MII TRANSMIT TIMING (100BASE-TX) PARAMETERS Parameter Description Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.
KSZ8041TL/FTL/MLL 7.6 RMII Timing FIGURE 7-6: RMII TIMING – DATA RECEIVED FROM RMII tcyc T ra n s m it T im in g REFCLK t1 t2 TX_EN T X D [1 :0 ] FIGURE 7-7: RMII TIMING – DATA INPUT TO RMII Receive Tim ing tcyc REFCLK CRSDV RXD[1:0] tod TABLE 7-6: RMII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units — 20 — ns tCYC Clock cycle t1 Setup time 4 — — ns t2 Hold time 2 — — ns Output delay 3 — 9 ns tOD 2017 Microchip Technology Inc.
KSZ8041TL/FTL/MLL 7.7 SMII Timing FIGURE 7-8: SMII TIMING – DATA RECEIVED FROM SMII Transmit Timing CLOCK tHU SYNC TX tSU FIGURE 7-9: SMII TIMING – DATA INPUT TO SMII Receive Timing CLOCK tOD SYNC RX TABLE 7-7: SMII TIMING PARAMETERS Parameter Description Min. Typ. Max. Units tSU Setup time 1.5 — — ns tHD Hold time 1.0 — — ns tOD Output delay 4.0 — 5.0 ns DS00002436B-page 50 2017 Microchip Technology Inc.
KSZ8041TL/FTL/MLL 7.8 Auto-Negotiation Timing FIGURE 7-10: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING A u to -N eg o tiatio n F ast L in k P u ls e (F L P ) T im in g FLP B u rst FLP B u rst T X + /T X - t F LP W tB T B C lo c k P u ls e D a ta P u ls e tP W tP W T X + /T X - D a ta P u lse C lo ck P u ls e tC T D tC T C TABLE 7-8: AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS Parameter Description tBTB tFLPW Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.9 MDC/MDIO Timing FIGURE 7-11: MDC/MDIO TIMING tP MDC tMD1 MDIO (PHY input) tMD2 Valid Data Valid Data tMD3 MDIO (PHY output) TABLE 7-9: MDC/MDIO TIMING PARAMETERS Parameter Description tP Valid Data Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.10 Reset Timing The KSZ8041TL/FTL/MLL reset timing requirement is summarized in the following figure and table. FIGURE 7-12: RESET TIMING Supply Voltage tsr RST# tcs tch Strap-In Value trc Strap-In / Output Pin TABLE 7-10: RESET TIMING PARAMETERS Parameter Description Min. Typ. Max.
KSZ8041TL/FTL/MLL 7.11 Reset Circuit The following reset circuit is recommended for powering up the KSZ8041TL/FTL/MLL if reset is triggered by the power supply. FIGURE 7-13: RECOMMENDED RESET CIRCUIT 3.3V D1: 1N4148 D1 R 10Nȍ KSZ8041TL/FTL/M LL RST# C 10μF The following reset circuit is recommended for applications where reset is driven by another device (e.g., CPU or FPGA). At power-on-reset, R, C and D1 provide the necessary ramp rise time to reset the KSZ8041TL/FTL/MLL device.
KSZ8041TL/FTL/MLL FIGURE 7-15: REFERENCE CIRCUITS FOR LED STRAPPING PINS 3.3V Pull-Up Nȍ ȍ KSZ8041TL/FTL/MLL LED pin 3.3V Float ȍ KSZ8041TL/FTL/MLL LED pin 3.3V Pull-Down ȍ KSZ8041TL/FTL/MLL LED pin Nȍ 2017 Microchip Technology Inc.
KSZ8041TL/FTL/MLL 8.0 SELECTION OF ISOLATION TRANSFORMERS A 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke is recommended for exceeding FCC requirements. Table 8-1 lists recommended transformer characteristics. TABLE 8-1: TRANSFORMER SELECTION CRITERIA Parameter Value Test Conditions Turns Ratio 1 CT:1 CT — Open-Circuit Inductance (min.) 350 µH 100 mV, 100 kHz, 8 mA Leakage Inductance (max.) 0.4 µH 1 MHz (min.
KSZ8041TL/FTL/MLL 9.0 PACKAGE OUTLINE FIGURE 9-1: Note: 48-LEAD LQFP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. 2017 Microchip Technology Inc.
KSZ8041TL/FTL/MLL FIGURE 9-2: Note: 48-LEAD TQFP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND PATTERN For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging. DS00002436B-page 58 2017 Microchip Technology Inc.
KSZ8041TL/FTL/MLL APPENDIX A: TABLE A-1: DATA SHEET REVISION HISTORY REVISION HISTORY Revision Section/Figure/Entry Correction DS00002436B (10-04-17) Section 5.0, Operational Characteristics Moved Maximum Junction Temperature information from Section 5.1, Absolute Maximum Ratings* to Section 5.2, Operating Ratings** for consistency with previous releases. Rev. A (7-11-17) __ Converted Micrel data sheet KSZ8041TL/FTL/MLL to Microchip DS00002436B. Minor text changes throughout.
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KSZ8041TL/FTL/MLL PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Examples: PART NO.
KSZ8041TL/FTL/MLL Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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