Datasheet

 2014 Microchip Technology Inc. DS20005323A-page 13
HV9910C
FIGURE 4-3: 8-LEAD SOIC (NARROW BODY) PACKAGE OUTLINE (SG)
Notes:
1. This chamfer feature is optional. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier
can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.
1
8
EE1
D
e
b
A
A2
A1
Seating
Plane
A
A
Top View
Side View
View B
Note 1
(Index Area
D/2 x E1/2)
View A-A
8
1
Bottom View
D1
E2
Exposed
Thermal Pad Zone
Seating
Plane
Gauge
Plane
L
L1
L2
View B
θ1
θ
h
h
Note 1
Symbol A A1 A2 b D D1 E E1 E2 e h L L1 L2 1
Dimension
(mm)
MIN 1.25* 0.00 1.25 0.31 4.80* 3.30† 5.80* 3.80* 2.29†
1.27
BSC
0.25 0.40
1.04
REF
0.25
BSC
0° 5°
NOM - - - - 4.90 - 6.00 3.90 - - - - -
MAX 1.70 0.15 1.55* 0.51 5.00* 3.81† 6.20* 4.00* 2.79† 0.50 1.27 8° 15°
JEDEC Registration MS-012, Variation BA, Issue E, Sep 2005.
* This dimension is not specified in the JEDEC drawing.
† This dimension differs from the JEDEC drawing.
Drawings not to scale.