User Guide

5. Testbench
Testbench is provided to check the functionality of the H.264 Encoder IP.
5.1 Simulation
The simulation uses a 432 × 240 image in the YCbCr422 format represented by two files, each for Y and C as input
and generates a H.264 file format containing two frames. The following steps describe how to simulate the core
using the testbench.
1. Go to Libero SoC Catalog > View > Windows > Catalog, and then expand Solutions-Video. Double click
H264_Encoder, and then click OK.
Figure 5-1. H.264 Encoder IP Core in Libero SoC Catalog
2. To generate the required SmartDesign for the H.264 Encoder IP simulation, click Libero Project
> Execute script. Browse to script ..\<Project_name>\component\Microchip\SolutionCore\
H264_Encoder\ <H264 IP version>\scripts\H264_SD.tcl, and then click Run .
Figure 5-2. Execute Script Run
The default AXI data bus width is 512. If the H.264 Encoder IP is configured for 256/128 bus widths, type
AXI_DATA_WIDTH:256 or AXI_DATA_WIDTH:128 in the Arguments field.
The SmartDesign appears. See the following figure.
Testbench
© 2022 Microchip Technology Inc.
and its subsidiaries
User Guide
DS50003366B-page 11