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H.264 Encoder User Guide

Introduction

H.264 is a popular video compression standard for compression of digital video. It is also known as MPEG-4 Part10

or Advanced Video Coding (MPEG-4 AVC). H.264 uses block-wise approach for compressing the video where the

block size is defined as 16 x 16 and is called a macro block. The compression standard supports various profiles

that define the compression ratio and complexity of the implementation. The video frames, to be compressed, are

treated as I frame, P frame, and B frame. An I frame is an intra-coded frame where compression is done by using the

information contained within the frame. No other frames are required to decode an I frame. A P frame is compressed

by using the changes with respect to an earlier frame that can be an I frame or a P frame. The compression of B

frame is done by using the motion changes with respect to both an earlier frame and an upcoming frame.

The I and P frame compression process has four stages:

• Intra/Inter prediction

• Integer transformation

• Quantization

• Entropy encoding

H.264 supports two types of encoding:

• Context Adaptive Variable Length Coding (CAVLC)

• Context Adaptive Binary Arithmetic Coding (CABAC)

The current version of H.264 Encoder implements baseline profile and uses CAVLC for entropy encoding. Also,

H.264 Encoder supports encoding of I and P frames.

and its subsidiaries

User Guide

DS50003366B-page 1

Summary of content (22 pages)

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H.264 Encoder User Guide Introduction H.264 is a popular video compression standard for compression of digital video. It is also known as MPEG-4 Part10 or Advanced Video Coding (MPEG-4 AVC). H.264 uses block-wise approach for compressing the video where the block size is defined as 16 x 16 and is called a macro block. The compression standard supports various profiles that define the compression ratio and complexity of the implementation.
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Features H.264 Encoder has the following key features: • • • • • • • • • • • • Compresses YCbCr 420 video format Accepts YCbCr 422 video format as input Supports 8-bit for each component (Y, Cb, and Cr) Supports ITU-T H.
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Table of Contents Introduction.....................................................................................................................................................1 Features.................................................................................................................................................. 3 Supported Families................................................................................................................................. 3 1.
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Hardware Implementation 1. Hardware Implementation This section describes the different internal modules of the H.264 Encoder. Data input to the H.264 Encoder must be in the form of a raster scan image in the YCbCr 422 format. H.264 Encoder uses 422 formats as input and implements compression in 420 formats. The following figure shows the H.264 Encoder block diagram. Figure 1-1. H.264 Encoder - Modules 1.1 Intra Prediction H.
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Hardware Implementation 1.5 Motion Compensation The Motion compensation gets the motion vectors from the Motion Estimation block and finds the corresponding 8 x 8 block in the previous frame. 1.6 CAVLC H.264 uses two types of entropy encoding—CAVLC and CABAC. The IP uses CAVLC for encoding the quantized output. 1.
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Inputs and Outputs 2. 2.1 Inputs and Outputs This section describes the inputs and the outputs of the H.264 Encoder. Ports The following tables list the description of the input and the output ports of the H.264 Encoder. Table 2-1. Inputs and Outputs of H.
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Inputs and Outputs ...........continued Signal Name Direction Width Description DATA_O Output 16 H.264 encoded data output that contains NAL unit, slice header, SPS, PPS, and the encoded data of macro blocks. — Write channel bus to be connected with Video arbiter Write channel bus. This is available when the bus interface is selected for Arbiter Interface. — Read channel bus to be connected with Video arbiter Read channel bus.
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Clock Constraints 3. Clock Constraints The H.264 Encoder IP uses PIX_CLK_I and DDR_CLK_I clock inputs. Use the clock grouping constraints for place and routing and verify timing as the IP implements the clock domain crossing logic. © 2022 Microchip Technology Inc.
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Installation Instructions 4. Installation Instructions H.264 Encoder core must be installed to the IP Catalog of the Libero® SoC software. This is done automatically through the IP Catalog update function in the Libero SoC software, or the IP core can be manually downloaded from the catalog. Once the IP core is installed in the Libero SoC software IP Catalog, the core can be configured, generated, and instantiated within SmartDesign for inclusion in the Libero project. © 2022 Microchip Technology Inc.
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Testbench 5. Testbench 5.1 Simulation Testbench is provided to check the functionality of the H.264 Encoder IP. The simulation uses a 432 × 240 image in the YCbCr422 format represented by two files, each for Y and C as input and generates a H.264 file format containing two frames. The following steps describe how to simulate the core using the testbench. 1. Go to Libero SoC Catalog > View > Windows > Catalog, and then expand Solutions-Video. Double click H264_Encoder, and then click OK. Figure 5-1.
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Testbench Figure 5-3. Top SmartDesign 3. On the Files tab, click simulation > Import Files. Figure 5-4. Import Files 4. Import the H264_sim_data_in_y.txt, H264_sim_data_in_c.txt file and the H264_sim_refOut.txt file from the following path: ..\\component\Microchip\SolutionCore\ H264_Encoder\\Stimulus. 5. To import a different file, browse the folder that contains the required file, and click Open. The imported file is listed under simulation, see the following figure.
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Testbench Figure 5-5. Imported Files 6. On the Stimulus Hierarchy tab, click H264_Encoder_tb (H264_Encoder_tb. v) > Simulate Pre-Synth Design > Open Interactively. The IP is simulated for two frames. Figure 5-6. Simulating Pre-Synthesis Design ModelSim opens with the testbench file as shown in the following figure. © 2022 Microchip Technology Inc.
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Testbench Figure 5-7. ModelSim Simulation Window Important: If the simulation is interrupted due to the run time limit specified in the DO file, use the run -all command to complete the simulation. © 2022 Microchip Technology Inc.
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Resource Utilization 6. Resource Utilization H.264 Encoder is implemented in the PolarFire SoC FPGA (MPFS250T-1FCG1152I package) and generates compressed data by using 4:2:2 sampling of input data. Table 6-1. Resource Utilization for H.264 Encoder Resource Usage 4 Look-Up Tables (LUTs) 69092 D Flip Flops (DFFs) 65522 Static Random Access Memory (LSRAM) 232 uSRAM 30 Math blocks 19 Interface 4-input LUTs 9396 Interface DFFs 9396 © 2022 Microchip Technology Inc.
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Configuration Parameters 7. Configuration Parameters The following table lists the description of the generic configuration parameters used in the hardware implementation of the H.264 Encoder, which can vary based on the application requirements. Table 7-1. Configuration Parameters Name 7.1 Description DDR_AXI_DATA_WIDTH Defines the DDR AXI data width.
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License 8. License H.264 Encoder is provided in encrypted form only under license. Encrypted RTL source code is license-locked and must be purchased separately. You can perform simulation, synthesis, layout, and program the Field Programmable Gate Array (FPGA) silicon using the Libero design suite. Evaluation license is provided for free to check the H.264 Encoder features. The evaluation license expires after an hour’s use on the hardware. © 2022 Microchip Technology Inc.
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Revision History 9. Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Table 9-1. Revision History Revision Date B 09/2022 A 07/2022 Description • • • • • • Initial release. © 2022 Microchip Technology Inc. and its subsidiaries Updated Features section. Updated the width of DATA_O output signal from 8 to 16, see Table 2-1. Updated Figure 7-1. Updated 8. License section.
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Microchip FPGA Support Microchip FPGA products group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, and worldwide sales offices. Customers are suggested to visit Microchip online resources prior to contacting support as it is very likely that their queries have been already answered. Contact Technical Support Center through the website at www.microchip.com/support.
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• • • • Microchip products meet the specifications contained in their particular Microchip Data Sheet. Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
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