Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 90  2013-2014 Microchip Technology Inc.
4.3.1 PAGED MEMORY SCHEME
The dsPIC33EPXXXGM3XX/6XX/7XX architecture
extends the available Data Space through a paging
scheme, which allows the available Data Space to be
accessed using MOV instructions in a linear fashion for
pre- and post-modified Effective Addresses (EA). The
upper half of the Base Data Space address is used in
conjunction with the Data Space Page registers, the
10-bit Data Space Read Page register (DSRPAG) or
the 9-bit Data Space Write Page register (DSWPAG),
to form an Extended Data Space (EDS) address, or
Program Space Visibility (PSV) address. The Data
Space Page registers are located in the SFR space.
Construction of the EDS address is shown in
Figure 4-8. When DSRPAG<9> = 0 and the base
address bit, EA<15> = 1, the DSRPAG<8:0> bits are
concatenated onto EA<14:0> to form the 24-bit EDS
read address. Similarly, when the base address bit,
EA<15> =1, the DSWPAG<8:0> bits are concatenated
onto EA<14:0> to form the 24-bit EDS write address.
FIGURE 4-8: EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
1
DSRPAG<8:0>
9 Bits
EA
15 Bits
Select
Byte24-Bit EDS EA
Select
EA
(DSRPAG = Don’t Care)
No EDS Access
Select16-Bit DS EA
Byte
EA<15> = 0
DSRPAG
0
EA<15>
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
= 1?
DSRPAG<9>
Y
N
Generate
PSV Address
0