Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 9
dsPIC33EPXXXGM3XX/6XX/7XX
TABLE 2: PIN NAMES: dsPIC33EP128/256/512GM310/710 DEVICES
(1,2,3)
Pin # Full Pin Name Pin # Full Pin Name
A1 TDO/PWM4H/PMD4/RA10 E8 AN47/INT4/RA15
A2 RPI45/PWM2L/CTPLS/PMD3/RB13 E9 RPI72/RD8
A3 RP125/RG13 E10 PGED2/ASDA2/RP37/RB5
A4 RP42/PWM3H/PMD0/RB10 E11 AN46/INT3/RA14
A5 RPI112/RG0 F1 MCLR
A6 RP97/RF1 F2 AN17/ASDA1/RP120/PMA3/RG8
A7 V
DD F3 AN16/RPI121/PMA2/RG9
A8 No Connect F4 AN18/ASCL1/RPI119/PMA4/RG7
A9 RPI76/RD12 F5 V
SS
A10 RP54/RC6 F6 No Connect
A11 TMS/OA5IN-/AN27/C5IN1-/RP41/RB9 F7 No Connect
B1 No Connect F8 V
DD
B2 AN23/RP127/RG15 F9 AN49/OSC1/CLKI/RPI60/RC12
B3 RPI44/PWM2H/PMD2/RB12 F10 V
SS
B4 RP43/PWM3L/PMD1/RB11 F11 OSC2/CLKO/RPI63/RC15
B5 RF7 G1 AN21/RE8
B6 RPI96/RF0 G2 AN20/RE9
B7 V
CAP G3 AN22/RG10
B8 RP69/PMRD/RD5 G4 No Connect
B9 RP55/PMBE/RC7 G5 V
DD
B10 VSS G6 VSS
B11 TCK/AN26/CVREF1O/SOSCO/RP40/T4CK/RB8 G7 VSS
C1 RPI46/PWM1H/T3CK/T7CK/PMD6/RB14 G8 No Connect
C2 V
DD G9 AN45/RF5
C3 RPI124/RG12 G10 AN43/RG3
C4 RP126/RG14 G11 AN44/RF4
C5 RF6 H1 AN10/RPI28/RA12
C6 No Connect H2 AN9/RPI27/RA11
C7 RP57/RC9 H3 No Connect
C8 RP56/PMWR/RC8 H4 No Connect
C9 No Connect H5 No Connect
C10 SOSCI/RPI61/RC13 H6 V
DD
C11 AN48/CVREF2O/RPI58/PMCS1/RC10 H7 No Connect
D1 PWM5L/RD1 H8 AN28/SDI1/RPI25/RA9
D2 RPI47/PWM1L/T5CK/T6CK/PMD7/RB15 H9 AN29/SCK1/RPI51/RC3
D3 TDI/PWM4L/PMD5/RA7 H10 AN31/SCL1/RPI53/RC5
D4 No Connect H11 AN42/RG2
D5 No Connect J1 OA2OUT/AN0/C2IN4-/C4IN3-/RPI16/RA0
D6 No Connect J2 OA2IN+/AN1/C2IN3-/C2IN1+/RPI17/RA1
D7 RP70/RD6 J3 PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RTCC/RB3
D8 RPI77/RD13 J4 AV
DD
D9 OA5OUT/AN25/C5IN4-/RP39/INT0/RB7 J5 AN11/C1IN2-/U1CTS/FLT4/PMA12/RC11
D10 No Connect J6 AN35/RG11
D11 PGEC2/ASCL2/RP38/PMCS2/RB6 J7 AN12/C2IN2-/C5IN2-/U2RTS
/BCLK2/FLT5/PMA11/RE12
Note 1: The RPn/RPIn pins can be used by any remappable peripheral with some limitation. See Section 11.4 “Peripheral Pin Select (PPS)” for
available peripherals and for information on limitations.
2: Every I/O port pin (RAx-RGx) can be used as a Change Notification pin (CNAx-CNGx). See Section 11.0 “I/O Ports” for more information.
3: The availability of I
2
C™ interfaces varies by device. Selection (SDAx/SCLx or ASDAx/ASCLx) is made using the device Configuration bits,
ALTI2C1 and ALTI2C2 (FPOR<5:4>). See Section 30.0 “Special Features” for more information.