Datasheet

ManualsBrandsMicrochip ManualsEmbedded Processors & ControllersMicrocontroller 8 Bit TQFP-44

 2013-2014 Microchip Technology Inc. DS70000689D-page 81

dsPIC33EPXXXGM3XX/6XX/7XX

TABLE 4-41: OP AMP/COMPARATOR REGISTER MAP

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CMSTAT 0A80 PSIDL — — C5EVT C4EVT C3EVT C2EVT C1EVT — — — C5OUT C4OUT C3OUT C2OUT C1OUT

0000

CVR1CON 0A82 — — — — CVRR1 VREFSEL — — CVREN CVROE CVRR0 CVRSS CVR3 CVR2 CVR1 CVR0

0000

CM1CON 0A84 CON COE CPOL — — OPMODE CEVT COUT EVPOL1 EVPOL0 —CREF— — CCH1 CCH0

0000

CM1MSKSRC 0A86 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0

0000

CM1MSKCON 0A88 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

0000

CM1FLTR 0A8A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0

0000

CM2CON 0A8C CON COE CPOL — — OPMODE CEVT COUT EVPOL1 EVPOL0 —CREF— — CCH1 CCH0

0000

CM2MSKSRC 0A8E — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0

0000

CM2MSKCON 0A90 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

0000

CM2FLTR 0A92 — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0

0000

CM3CON 0A94 CON COE CPOL — — OPMODE CEVT COUT EVPOL1 EVPOL0 —CREF— — CCH1 CCH0

0000

CM3MSKSRC 0A96 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0

0000

CM3MSKCON 0A98 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

0000

CM3FLTR 0A9A — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0

0000

CM4CON 0A9C CON COE CPOL — — — CEVT COUT EVPOL1 EVPOL0 —CREF— — CCH1 CCH0

0000

CM4MSKSRC 0A9E — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0

0000

CM4MSKCON 0AA0 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

0000

CM4FLTR 0AA2 — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0

0000

CM5CON 0AA4 CON COE CPOL — — OPMODE CEVT COUT EVPOL1 EVPOL0 —CREF— — CCH1 CCH0

0000

CM5MSKSRC 0AA6 — — — — SELSRCC3 SELSRCC2 SELSRCC1 SELSRCC0 SELSRCB3 SELSRCB2 SELSRCB1 SELSRCB0 SELSRCA3 SELSRCA2 SELSRCA1 SELSRCA0

0000

CM5MSKCON 0AA8 HLMS — OCEN OCNEN OBEN OBNEN OAEN OANEN NAGS PAGS ACEN ACNEN ABEN ABNEN AAEN AANEN

0000

CM5FLTR 0AAA — — — — — — — — — CFSEL2 CFSEL1 CFSEL0 CFLTREN CFDIV2 CFDIV1 CFDIV0

0000

CVR2CON 0AB4 — — — — CVRR1 VREFSEL — — CVREN CVROE CVRR0 CVRSS CVR3 CVR2 CVR1 CVR0

0000

Legend:

— = unimplemented, read as ‘

’. Reset values are shown in hexadecimal.