Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 73

dsPIC33EPXXXGM3XX/6XX/7XX

TABLE 4-29: PROGRAMMABLE CRC REGISTER MAP

C2RXF11SID 056C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0 — EXIDE —EID17EID16xxxx

C2RXF11EID 056E EID<15:0> xxxx

C2RXF12SID 0570 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

—MIDE—EID17EID16xxxx

C2RXF12EID 0572 EID<15:0> xxxx

C2RXF13SID 0574 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

—MIDE—EID17EID16xxxx

C2RXF13EID 0576 EID<15:0> xxxx

C2RXF14SID 0578 SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

—MIDE—EID17EID16xxxx

C2RXF14EID 057A EID<15:0> xxxx

C2RXF15SID 057C SID10 SID9 SID8 SID7 SID6 SID5 SID4 SID3 SID2 SID1 SID0

—MIDE—EID17EID16xxxx

C2RXF15EID 057E EID<15:0> xxxx

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CRCCON1 0640 CRCEN

— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000

CRCCON2 0642

— — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000

CRCXORL 0644 X<15:1>

— 0000

CRCXORH 0646 X<31:16> 0000

CRCDATL 0648 CRC Data Input Low Word Register 0000

CRCDATH 064A CRC Data Input High Word Register 0000

CRCWDATL 064C CRC Result Low Word Register 0000

CRCWDATH 064E CRC Result High Word Register 0000

Legend: — = unimplemented, read as ‘0’. Shaded bits are not used in the operation of the programmable CRC module.

TABLE 4-28: CAN2 REGISTER MAP WHEN WIN (C1CTRL<0>) = 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES

(1)

(CONTINUED)

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: These registers are not present on dsPIC33EPXXXGM3XX devices.