Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 68 2013-2014 Microchip Technology Inc.
TABLE 4-23: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 OR 1 FOR dsPIC33EPXXXGM60X/7XX DEVICES
(1)
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
C1CTRL1 0400 CSIDL ABAT CANCKS REQOP2 REQOP1 REQOP0 OPMODE2 OPMODE1 OPMODE0 —CANCAP —WIN
0480
C1CTRL2 0402 DNCNT<4:0>
0000
C1VEC 0404 FILHIT4 FILHIT3 FILHIT2 FILHIT1 FILHIT0 ICODE6 ICODE5 ICODE4 ICODE3 ICODE2 ICODE1 ICODE0
0040
C1FCTRL 0406 DMABS2 DMABS1 DMABS0 FSA4 FSA3 FSA2 FSA1 FSA0
0000
C1FIFO 0408 FBP5 FBP4 FBP3 FBP2 FBP1 FBP0 FNRB5 FNRB4 FNRB3 FNRB2 FNRB1 FNRB0
0000
C1INTF 040A TXBO TXBP RXBP TXWAR RXWAR EWARN IVRIF WAKIF ERRIF FIFOIF RBOVIF RBIF TBIF
0000
C1INTE 040C IVRIE WAKIE ERRIE FIFOIE RBOVIE RBIE TBIE
0000
C1EC 040E TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0 RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1RERRCNT0
0000
C1CFG1 0410 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0
0000
C1CFG2 0412 —WAKFIL SEG2PH2 SEG2PH1 SEG2PH0 SEG2PHTS SAM SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 PRSEG0
0000
C1FEN1 0414 FLTEN<15:0>
FFFF
C1FMSKSEL1 0418 F7MSK1 F7MSK0 F6MSK1 F6MSK0 F5MSK1 F5MSK0 F4MSK1 F4MSK0 F3MSK1 F3MSK0 F2MSK1 F2MSK0 F1MSK1 F1MSK0 F0MSK1 F0MSK0
0000
C1FMSKSEL2 041A F15MSK1 F15MSK0 F14MSK1 F14MSK0 F13MSK1 F13MSK0 F12MSK1 F12MSK0 F11MSK1 F11MSK0 F10MSK1 F10MSK0 F9MSK1 F9MSK0 F8MSK1 F8MSK0
0000
Legend:
— = unimplemented, read as
0
’. Reset values are shown in hexadecimal.
Note 1:
These registers are not present on dsPIC33EPXXXGM3XX devices.
TABLE 4-24: CAN1 REGISTER MAP WHEN WIN (C1CTRL<0>) = 0 FOR dsPIC33EPXXXGM60X/7XX DEVICES
(1)
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
0400-
041E
See definition when WIN = x
C1RXFUL1 0420 RXFUL<15:0> 0000
C1RXFUL2 0422 RXFUL<31:16> 0000
C1RXOVF1 0428 RXOVF<15:0> 0000
C1RXOVF2 042A RXOVF<31:16> 0000
C1TR01CON 0430 TXEN1 TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1 TX1PRI1 TX1PRI0 TXEN0 TXABAT0 TXLARB0 TXERR0 TXREQ0 RTREN0 TX0PRI1 TX0PRI0 0000
C1TR23CON 0432 TXEN3 TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3 TX3PRI1 TX3PRI0 TXEN2 TXABAT2 TXLARB2 TXERR2 TXREQ2 RTREN2 TX2PRI1 TX2PRI0 0000
C1TR45CON 0434 TXEN5 TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5 TX5PRI1 TX5PRI0 TXEN4 TXABAT4 TXLARB4 TXERR4 TXREQ4 RTREN4 TX4PRI1 TX4PRI0 0000
C1TR67CON 0436 TXEN7 TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7 TX7PRI1 TX7PRI0 TXEN6 TXABAT6 TXLARB6 TXERR6 TXREQ6 RTREN6 TX6PRI1 TX6PRI0 xxxx
C1RXD 0440 CAN1 Receive Data Word xxxx
C1TXD 0442 CAN1 Transmit Data Word xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: These registers are not present on dsPIC33EPXXXGM3XX devices.