Datasheet

ManualsBrandsMicrochip ManualsEmbedded Processors & ControllersMicrocontroller 8 Bit TQFP-44

dsPIC33EPXXXGM3XX/6XX/7XX

DS70000689D-page 64  2013-2014 Microchip Technology Inc.

TABLE 4-20: SPI1, SPI2 AND SPI3 REGISTER MAP

TABLE 4-19: UART3 AND UART4 REGISTER MAP

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

U3MODE 0250 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U3STA 0252 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U3TXREG 0254

— — — — — — — UART3 Transmit Register xxxx

U3RXREG 0256

— — — — — — — UART3 Receive Register 0000

U3BRG 0258 Baud Rate Generator Prescaler 0000

U4MODE 02B0 UARTEN

— USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL1 PDSEL0 STSEL 0000

U4STA 02B2 UTXISEL1 UTXINV UTXISEL0

— UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA 0110

U4TXREG 02B4

— — — — — — — UART4 Transmit Register xxxx

U4RXREG 02B6

— — — — — — — UART4 Receive Register 0000

U4BRG 02B8 Baud Rate Generator Prescaler 0000

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Name

Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

SPI1STAT 0240 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI1CON1 0242

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI1CON2 0244 FRMEN SPIFSD FRMPOL

— — — — — — — — — — — FRMDLY SPIBEN 0000

SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register 0000

SPI2STAT 0260 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI2CON1 0262

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI2CON2 0264 FRMEN SPIFSD FRMPOL

— — — — — — — — — — — FRMDLY SPIBEN 0000

SPI2BUF 0268 SPI2 Transmit and Receive Buffer Register 0000

SPI3STAT 02A0 SPIEN

— SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF 0000

SPI3CON1 02A2

— — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 0000

SPI3CON2 02A4 FRMEN SPIFSD FRMPOL

— — — — — — — — — — — FRMDLY SPIBEN 0000

SPI3BUF 02A8 SPI3 Transmit and Receive Buffer Register 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.