Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 533
dsPIC33EPXXXGM3XX/6XX/7XX
AUXCONx (PWMx Auxiliary Control)........................ 254
CHOP (PWMx Chop Clock Generator)..................... 241
CLKDIV (Clock Divisor)............................................. 148
CM4CON (Op Amp/Comparator 4 Control) .............. 373
CMSTAT (Op Amp/Comparator Status) ................... 370
CMxCON (Op Amp/Comparator x
Control, x = 1, 2, 3 or 5) .................................... 371
CMxFLTR (Comparator x Filter Control)................... 379
CMxMSKCON (Comparator x Mask
Gating Control) ................................................. 377
CMxMSKSRC (Comparator x Mask Source
Select Control) .................................................. 375
CORCON (Core Control) .................................... 33, 122
CRCCON1 (CRC Control 1) ..................................... 407
CRCCON2 (CRC Control 2) ..................................... 408
CRCXORH (CRC XOR Polynomial High)................. 409
CRCXORL (CRC XOR Polynomial Low) .................. 409
CTMUCON1 (CTMU Control Register 1).................. 323
CTMUCON2 (CTMU Control Register 2).................. 324
CTMUICON (CTMU Current Control) ....................... 326
CVR1CON (Comparator Voltage
Reference Control 1) ........................................ 380
CVR2CON (Comparator Voltage
Reference Control 2) ........................................ 381
CxBUFPNT1 (CANx Filters 0-3
Buffer Pointer 1)................................................ 306
CxBUFPNT2 (CANx Filters 4-7
Buffer Pointer 2)................................................ 307
CxBUFPNT3 (CANx Filters 8-11
Buffer Pointer 3)................................................ 307
CxBUFPNT4 (CANx Filters 12-15
Buffer Pointer 4)................................................ 308
CxCFG1 (CANx Baud Rate Configuration 1)............ 304
CxCFG2 (CANx Baud Rate Configuration 2)............ 305
CxCTRL1 (CANx Control 1)...................................... 297
CxCTRL2 (CANx Control 2)...................................... 298
CxEC (CANx Transmit/Receive Error Count) ........... 304
CxFCTRL (CANx FIFO Control) ............................... 300
CxFEN1 (CANx Acceptance Filter Enable 1)............ 306
CxFIFO (CANx FIFO Status) .................................... 301
CxFMSKSEL1 (CANx Filters 7-0
Mask Selection 1) ............................................. 310
CxFMSKSEL2 (CANx Filters 15-8
Mask Selection 2) ............................................. 311
CxINTE (CANx Interrupt Enable) .............................. 303
CxINTF (CANx Interrupt Flag) .................................. 302
CxRXFnEID (CANx Acceptance Filter n
Extended Identifier)........................................... 309
CxRXFnSID (CANx Acceptance Filter n
Standard Identifier) ........................................... 309
CxRXFUL1 (CANx Receive Buffer Full 1)................. 313
CxRXFUL2 (CANx Receive Buffer Full 2)................. 313
CxRXMnEID (CANx Acceptance Filter Mask n
Extended Identifier)........................................... 312
CxRXMnSID (CANx Acceptance Filter Mask n
Standard Identifier) ........................................... 312
CxRXOVF1 (CANx Receive Buffer Overflow 1)........ 314
CxRXOVF2 (CANx Receive Buffer Overflow 2)........ 314
CxTRmnCON (CANx TX/RX Buffer mn Control) ...... 315
CxVEC (CANx Interrupt Code) ................................. 299
DCICON1 (DCI Control 1)......................................... 344
DCICON2 (DCI Control 2)......................................... 345
DCICON3 (DCI Control 3)......................................... 346
DCISTAT (DCI Status).............................................. 347
DEVID (Device ID) .................................................... 415
DEVREV (Device Revision)...................................... 415
DMALCA (DMA Last Channel Active Status) ........... 140
DMAPPS (DMA Ping-Pong Status) .......................... 141
DMAPWC (DMA Peripheral Write
Collision Status)................................................ 138
DMARQC (DMA Request Collision Status) .............. 139
DMAxCNT (DMA Channel x Transfer Count)........... 136
DMAxCON (DMA Channel x Control)....................... 132
DMAxPAD (DMA Channel x
Peripheral Address).......................................... 136
DMAxREQ (DMA Channel x IRQ Select) ................. 133
DMAxSTAH (DMA Channel x
Start Address A, High)...................................... 134
DMAxSTAL (DMA Channel x
Start Address A, Low)....................................... 134
DMAxSTBH (DMA Channel x
Start Address B, High)...................................... 135
DMAxSTBL (DMA Channel x
Start Address B, Low)....................................... 135
DSADRH (DMA Most Recent RAM
High Address)................................................... 137
DSADRL (DMA Most Recent RAM
Low Address).................................................... 137
DTRx (PWMx Dead-Time)........................................ 246
FCLCONx (PWMx Fault Current-Limit Control)........ 250
I2CxCON (I2Cx Control)........................................... 283
I2CxMSK (I2Cx Slave Mode Address Mask)............ 287
I2CxSTAT (I2Cx Status) ........................................... 285
ICxCON1 (Input Capture x Control 1)....................... 220
ICxCON2 (Input Capture x Control 2)....................... 221
INDXxCNTH (Index Counter x High Word) .............. 267
INDXxCNTL (Index Counter x Low Word)................ 267
INDXxHLD (Index Counter x Hold)........................... 268
INTCON1 (Interrupt Control 1) ................................. 123
INTCON2 (Interrupt Control 2) ................................. 125
INTCON3 (Interrupt Control 3) ................................. 126
INTCON4 (Interrupt Control 4) ................................. 126
INTTREG (Interrupt Control and Status) .................. 127
INTxHLDH (Interval Timerx Hold High Word)........... 272
INTxHLDL (Interval Timerx Hold Low Word) ............ 272
INTxTMRH (Interval Timerx High Word) .................. 271
INTxTMRL (Interval Timerx Low Word).................... 271
IOCONx (PWMx I/O Control).................................... 248
LEBCONx (Leading-Edge Blanking Control x) ......... 252
LEBDLYx (Leading-Edge Blanking Delay x) ............ 253
MDC (PWMx Master Duty Cycle) ............................. 241
NVMADR (Nonvolatile Memory Lower Address)...... 107
NVMADRU (Nonvolatile Memory
Upper Address) ................................................ 107
NVMCON (Nonvolatile Memory (NVM) Control) ...... 105
NVMKEY (Nonvolatile Memory Key)........................ 108
NVMSRCADRH (Nonvolatile Data Memory
Upper Address) ................................................ 108
NVMSRCADRL (Nonvolatile Data Memory
Lower Address) ................................................ 109
OCxCON1 (Output Compare x Control 1) ................ 224
OCxCON2 (Output Compare x Control 2) ................ 226
OSCCON (Oscillator Control) ................................... 146
OSCTUN (FRC Oscillator Tuning)............................ 151
PADCFG1 (Pad Configuration Control)............ 387, 403
PDCx (PWMx Generator Duty Cycle)....................... 244
PHASEx (PWMx Primary Phase-Shift)..................... 245
PLLFBD (PLL Feedback Divisor) ............................. 150
PMADDR (Parallel Master Port Address)................. 400
PMAEN (Parallel Master Port Address Enable) ....... 401