Datasheet

dsPIC33EPXXXGM3XX/6XX/7XX
DS70000689D-page 504  2013-2014 Microchip Technology Inc.
TABLE 34-11: PLL CLOCK TIMING SPECIFICATIONS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +150°C
Param
No.
Symbol Characteristic Min Typ Max Units Conditions
HOS53 D
CLK CLKO Stability (Jitter)
(1)
-5 0.5 5 % Measured over 100 ms
period
Note 1: These parameters are characterized by similarity, but are not tested in manufacturing. This specification is
based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time
bases or communication clocks use this formula:
Peripheral Clock Jitter
DCLK
FOSC
Peripheral Bit Rate Clock
--------------------------------------------------------------


------------------------------------------------------------------------=
For example: FOSC = 32 MHz, DCLK = 5%, SPIx bit rate clock (i.e., SCKx) is 2 MHz.
SPI SCK Jitter
D
CLK
32 MHz
2 MHz
--------------------


------------------------------
5%
16
----------
5%
4
--------1.25%====
TABLE 34-12: INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +150°C
Param
No.
Characteristic Min Typ Max Units Conditions
Internal FRC Accuracy @ FRC Frequency = 7.3728 MHz
HF20 FRC -3 — +3 % -40°C  T
A +150°C VDD = 3.0-3.6V
TABLE 34-13: INTERNAL RC ACCURACY
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C  TA  +150°C
Param
No.
Characteristic Min Typ Max Units Conditions
LPRC @ 32.768 kHz
(1,2)
HF21 LPRC -30 — +30 % -40°C  TA +150°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
2: LPRC accuracy impacts the Watchdog Timer Time-out Period (TWDT1). See Section 30.5 “Watchdog
Timer (WDT)” for more information.