Datasheet

 2013-2014 Microchip Technology Inc. DS70000689D-page 47
dsPIC33EPXXXGM3XX/6XX/7XX
SR 0042 OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA N OV Z C 0000
CORCON 0044 VAR
— US1 US0 EDT DL1 DL2 DL0 SATA SATB SATDW ACCSAT IPL3 SFA RND IF 0020
MODCON 0046 XMODEN YMODEN
— — BWM3 BWM2 BWM1 BWM0 YWM3 YWM2 YWM1 YWM0 XWM3 XWM2 XWM1 XWM0 0000
XMODSRT 0048 XMODSRT<15:0>
— 0000
XMODEND 004A XMODEND<15:0>
— 0001
YMODSRT 004C YMODSRT<15:0>
— 0000
YMODEND 004E YMODEND<15:0>
— 0001
XBREV 0050 BREN XBREV<14:0> 0000
DISICNT 0052
— — DISICNT<13:0> 0000
TBLPAG 0054
— — — — — — — —TBLPAG<7:0>0000
MSTRPR 0058 MSTRPR<15:0> 0000
TABLE 4-1: CPU CORE REGISTER MAP (CONTINUED)
SFR
Name
Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
All
Resets
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.